Biography
Enrollment Date: 2005
Graduation Date:2010
Degree:Ph.D.
Defense Date:2010.06.12
Advisors:Zhihua Wang
Department:Institute of Microelectronics,Tsinghua University
Title of Dissertation/Thesis:A Research on Key Technologies for Sub-threhsold Integrated Circuit and a System Design of Balance Measurement for Artificial Joint Replacement
Abstract:
Integrated circuit is a key technology for realization of the mdeical microsystem. Low-power design technology becomes one of the necessary developments for mdeical microsystem because of the low-power demand. As one of low-power technologies, the sub-threshold circuit works under the sub-threshold voltage of the transistor. The sub-threshold ciruit has potential applications that don’t require high speed but power-stringent. Following the requirements by artificial joint replacement, this paper studies the design method of the sub-threhsold digital circuit and investigates other potential applications of the sub-threhsold circuit. More details about the results of the paper are listed as below. (1) A design method of the sub-threshold digital circuit is delivered. The method solves the nonlear modulation effect on the threshold by transistor size. Thus the tranditional desgn method can be applied to the sub-threshold circuit and the design difficults of the sub-threshold circuit are reduced. The method can increase speed, lower the leakage current and alleviate the senstivities to the voltage, temperature, transistor threshold and process varitaiton. (2) The standard cells design methods are investigated. A full UMC180nm sub-threshold digital standard library is founded by optimizing the size and structure to lower the power consumption and increase the speed of the cells. (3) The design method of sub-threshold SRAM cell is investigated. A 1K bit SRAM is constructed by using a type of 11T SRAM cell. The test results verified the function of the SRAM and shows that it has low leakage power consumption. (4) A system of balance measurement for artificial joint replacement is proposed. The article completed the system design and the verification of the front-end. The test results show that the performance of the front-end meets the system requirements. (5) A sub-threhsold 8051 core with 1K bit SRAM is designed by using sub-threshold standard library. The test results are summarized as follows. The memory part of the chip’s lowest operation voltage is 350mV, the frequency 165KHz, the leakage power 58nW, the dynamic power 385nW and EDP 13pJ/inst. The digital part can operate down to 250mV. Under 350mV, the average EDP is 3.75pJ/inst. The results show that the sub-threshold library has advantages of low-power consumption and high performance. (6) A test for light-powered RFID Tag is carried out. The 8051 core is powered by an integrated photo-sensitive diode under light. Under the light of 150 thousands of lux, the 8051 core can run at a rate up to 500KHz. The test result proves that it is possible to drive a RFID Tag by light.