Title：SRAM circuit device with divided bitline and two-stage sense amplifiers

Country：China

Patent No.：201110205980.5

Legal Status：Authorized

Inventor：Ming Liu, Hong Chen, Xiang Zheng, Huamin Cao, Zhiqiang Gao, Zhihua Wang

Assignee：Tsinghua University

Address：Tsinghua University,Haidian District Beijing 100084, China

Filing Date：2011-07-21

Issue Date：2013-09-04

The invention relates to a static random access memory (SRAM) circuit device employing hierarchical bit lines and a two-stage sensitive amplifier. The circuit device is divided into subarrays; in each subarray, each local bit line is hung with a SRAM unit correspondingly by using divided bit line number; a first stage sensitive amplifier has a latch type structure; two input nodes and output nodes of inverters which are crossed and coupled are respectively driven for a global bit line through a P-channel metal oxide semiconductor (PMOS) transistor, so a signal after amplification of local bitlines is not required to be buffered and used for directly driving the global bit line. Compared with the conventional scheme, the speed can be increased. A second stage sensitive amplifier adopts a pair of complementary differential amplifiers, starts working before the first stage sensitive amplifier is opened, responses to changes of the global bit line, and amplifies differential data on the global bit line to full amplitude for output. A complementary structure is adopted in the invention and favorable for latching of the data and final driving output; compared with the traditional structure, the circuit employing the hierarchical bit lines and a two-stage amplification mechanism has the advantages that: the access delay is reduced by 15 percent, and the speed of a SRAM is effectively increased.

Patent Certificate： PDF/Jpg