Biography
Enrollment Date: 2015
Graduation Date：2018
Degree：M.S.
Defense Date：2018.05.24
Advisors：Woogeun Rhee
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Robust Clock Generation/Modulation Using Bang-Bang Digital Phase-Locked Loops
Abstract:
Phase-locked loop (PLL) is a key building block in modern integrated circuits and systems, ranging from clock generation for digital systems, to clock and data recovery for wireline systems and frequency synthesizer for wireless systems. The design theory
and circuit topologies of conventional analog PLLs have already been quite mature such that excellent noise performance can be achieved. However, with the quick
development of CMOS technologies, the cost of analog circuits becomes much higher and its performance saturates or even degrades. Thus, it is necessary to digitize the analog PLLs.
Not suffering from the high linearity and fine resolution requirement of the time-to-digital converter (TDC), the digital PLL with a Bang-Bang phase detector enables an ultra-low voltage design. However, serious noise degradation is observed in
fractional-N mode and strong nonlinearity of the digital controlled oscillator (DCO) greatly degrades the modulation quality in two-point modulators.
This thesis focuses on the clock generation and modulation for wireline systems, with the emphasis on noise suppression and linearization of the DCO. The thesis has the following contributions:
The basic principle and of the all-digital PLL and its linear model are presented, from which the possible noise suppression techniques are analyzed. Then the PLL design aspects in communication systems are discussed as well as linearization techniques of DCO. Finally, the techniques of using a few-bit DTC for in-band noise customization and two-stage architecture for in-band noise reduction are proposed.
A 1.2GHz clock generator with the techniques of in-band noise customization and FIR filtering is implemented in 65nm CMOS. The measured 11dB in-band noise and 18dB out-of-band noise reductions are achieved with only 4b and 3b linearity requirements on the DTC and FIR filter, respectively.
A 5GHz clock modulator, combined with the techniques of two-stage structure and a few-bit DTC for moderate in-band noise performance and the technique of dual-loop structure for constant DCO gain without calibration, is also implemented in 65nm CMOS for PCIe applications.