Biography
Enrollment Date: 2015
Graduation Date：2018
Degree：M.S.
Defense Date：2018.05.24
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：12Bit 2Gsps Two-Channel Time-Interleaved Pipelined Analog-to-Digital Converter Design
Abstract:
High-performance analog-to-digital converters (ADCs) are core modules of base station communications, military radar, and high-speed measurement instruments. How to achieve high-speed and high-precision performance at the same time has always been a research hotspot in academia and industry. Researching this technology not only has academic significance and commercial value, but also has strategic significance.This thesis first researches the high-performance analog-to-digital converters appearing in the current industrial and academic sessions. It concludes that time-interleaving technology is the hot technology for high-performance converters. Then, various calibration methods for sampling time-skew are investigated and the Zero-Crossing (ZC) detection technique for time-skew calibration is focused on. At the same time, the sampling switches, reference buffer and calibration signal injection techniques in high performance converters are also researched.Based on the above research techniques and calibration algorithms, a 12bit-2Gsps two-channel time-interleaved pipelined ADC is designed. The ADC mainly includes the following features: (1) A level shifting transmission gate is used to strengthen the conduction of the MOS transistor, and the resistance value and the nonlinearity of the resistance when the switch is turned on are reduced, and in particular it is difficult to overcome the difficulty of the switch at the SS+ low temperature. (2) Using the front-end calibration method, the calibration signal generated by the VCO is injected through the bias source of the source follower, so as not to disconnect the original signal to ensure the integrity of the signal path; (3) A two-level shifting reference buffer circuit allows the reference buffer to have a larger output swing and faster response speed; (4) It has an input amplitude limit function to limit the residual amplifier by detecting the signal in the first stage circuit. Prevent the stage continue to enlarge and protect the thin gate MOS tube; (5)It has a fine variable delay line circuit, can reach 16fs step, used for time deviation analog correction; (6) stage circuit uses redundant technology and the actual output code are 14 bit for digital calibration. The simulation results show that under typical temperature and process conditions, SNDR = 72.86dB, SFDR = 76.47dB, and ENOB = 11.86bit under 804MHz input and 2GHz sampling. Especially in the condition of SS+low temperature, when Fin=86MHz，Fs=2GHz，the level shift switch was used to increase the SNDR, SFDR and ENOB of the circuit from 57.12dB, 59.73dB, and 9.20bit to 77.43dB,78.84dB and 12.57bit, respectively.The paper concludes with a 5bit-Flash-ADC with dynamic offset calibration comparator. For comparison, another 5-bit-Flash-ADC using comparator without offset calibration was designed. The test results show that the static characteristic DNL is reduced from 1.32LSB to 0.62LSB and the INL is reduced from 1.20LSB to 0.55LSB after the dynamic offset calibration technique is applied. At the input of 2.4MHz and the sampling frequency of 160MHz, the SNDR is increased from 26.25dB to 29.63dB, SFDR increased from 35.02dB to 43.61dB. Test results show that the calibration technique is effective.