Biography
Enrollment Date: 2014
Graduation Date：2017
Degree：M.S.
Defense Date：2017.05.25
Advisors：Baoyong Chi
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on Key Techniques of 77GHz FMCW Signal Generator
Abstract:
Only when secure and reliable automotive radar systems are realized can driverless technology be fully developed. The measurement accuracy of distance and speed in the widely used frequency-modulated-continuously-wave (FMCW) radar systems is limited by the FMCW modulation linearity, which depends on the modulation performance of the FMCW signal generator. With the continuous scaling down of CMOS technology, how to built a low-cost low-complexity high-performance FMCW signal generator becomes an obstacle that we have to overcome. This thesis focuses on the key design techniques of the 77-GHz mixed-mode FMCW signal generator.A FMCW signal generator based on bang-bang phase detector (BBPD) is proposed in this thesis, which avoids the large area occupied by the analog loop filter by using a digital loop filter. Through replacing the digitally-controlled oscillator (DCO) with a current digtal-to-analog converter (DAC) and a voltage-controlled oscillator (VCO), the proposed architecture has no need to perform a complex calibration to the DCO under the wide-bandwidth FMCW modulation. The quantization noise induced by BBPD is effectively reduced with a 1-bit single-loop 3rd-order ΔΣ modulator (SLDSM3) and the hybrid FIR filtering technique. The FMCW modulation linearity can be further improved by a type-III frequency ramp estimator.A linearized frequency-domain model is built for the proposed architecture to study the loop gain. An expression for the loop bandwidth can be derived with some proper simplifications. A behavioral modeling method based on MATLAB/Simulink is proposed. The specifications of each block can be decided through the time-domain behavioral simulations. The advantages of the 1-bit SLDSM3, the hybrid FIR filtering technique and the type-III frequency ramp estimator utilized in the proposed architecture can be verified through the behavioral simulations on the phase noise and FMCW modulation linearity.A prototype of the proposed FMCW signal generator is implemented in TSMC 65-nm CMOS technology. The phase noise at 1-MHz offset is -81.7 dBc/Hz and the reference spur is -66.3 dBc when the carrier frequency is 77 GHz. When the carrier frequency varies between 77 GHz and 79 GHz, the 1-MHz-offset phase noise varies from -81.7 dBc/Hz to -76.9 dBc/Hz, with the reference spur from -67.8 dBc to -65.2 dBc. The in-band phase noise is improved up to 25 dB with the 1-bit SLDSM3 and the hybrid FIR filtering technique. When FMCW modulation is performed with a bandwidth of 1.83 GHz and a period of 1 ms, the root-mean-square (rms) frequency error can be reduced from 682 kHz to 416 kHz with the 1-bit SLDSM3 and the hybrid FIR filtering technique, which can be further improved to 336 kHz with the type-III frequency ramp estimator.