题目/Title：A 5-bit Phase-Interpolator-Based Fractional-N Frequency Divider for Digital Phase-Locked Loops

作者/Author：林健夫,姜汉钧,池保勇
                        Jianfu Lin,Hanjun Jiang,Baoyong Chi

会议/Conference：ISCAS 2017

地点/Location：Baltimore, MD, USA

年份/Issue Date：2017.28-31 May

页码/pages：pp. 1 - 4

摘要/Abstract：
A fractional-N frequency divider based on a 5-bit phase interpolator (PI) is presented in this paper. A novel PI unit cell with the switched resistor loads is proposed to break the constraint brought by the variation of the common-mode output voltage, providing an extra design degree of freedom for the optimization. An all-digital phase rotating scheme is proposed to achieve an excellent balance between the robustness of the phase interpolation and the speed limitation of the synthesized phase control circuit. The proposed fractional-N frequency divider is designed in 65-nm CMOS technology, dissipating 1.13-1.3 mW from a 1.2-V supply with the quadrature input signals at 2.4 GHz. To further evaluate the influence of the PI non-linearity, a behavioral simulation model based on Simulink is built. The behavioral simulation results show that the in-band spur induced by the fractional-N frequency divider is -51.8 dBc.