Biography
Enrollment Date: 2012
Graduation Date：2015
Degree：M.S.
Defense Date：2015.06.02
Advisors：Zhihua Wang Baoyong Chi Ziqiang Wang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design of multimode polar transmitter RF chip for narrowband communications applications
Abstract:
The Internet of Things (IoT ) system which is widely used in the field of transport and logistics, health care fields and intelligent environment(home, office, factory), has a very broad application and market prospects. Various terminals of IoT sensing the environment or controlling other equipment，makes the wireless market in Sub-GHz frequency band have a not only huge but growing business opportunity. This kind of wireless terminals made the following requirements to wireless transmitter: narrow bandwidth and low-rate, low-power, multimode and configured.
Polar transmitter based on switch-mode power amplifier has great power advantages; single-point phase modulation architecture is enough for narrow-band and low-rate communications; this design tried to use more digital circuit rather than analog circuit, since the design of digital circuit is more flexible. This thesis studied the key technology on multimode Polar transmitter RF chip and designed an integrated RF chip verification platform established by MATLAB, Simulink, Quartus II，Cadence and other EDA tools, before integrating the polar RF transmitter into one chip.
The baseband part in this design accomplished encoding, modulation, shape-filtering and up-sampling filtering, then the signal was converted from cartesian coordinates to polar coordinate system, after which, the signal was presented as amplitude signal and phase signal. The phase signal, after differential operation, turned to be frequency signal. Then the frequency signal acted as the fractional part of the ΣΔ modulator. At this point, the output of the PLL was modulated carrier signal containing the phase signal. The amplitude path consisted of up-sampling filter, delay matching, gain controlling, temperature coding and a first-order ΣΔ modulator circuit. Meanwhile, in order to calibration the non-linear characteristic of the DPA, this thesis designed a pre-distortion algorithm which was based feedback and lookup table (LUT). DPA unit is equivalent to a multiplier, converting the amplitude and phase information into the complete modulated signal. Finally, the modulated signal went through synchronous demodulation, matched filtering and decode, and then presented in constellation diagram, compared with the original signal before the modulation contrast. Finally, the EVM was calculated, as a measure of various non-ideal features which effect the system.
The proposed design thesis completed behavioral modeling and simulation with MATLAB and Simulink. The simulation might be helpful in designing every module in the system. After completion of the RTL design of the digital circuit design, the digital circuit was verified by NCsim software and FPGA platform. The data band ranges from 1KHz to 24KHz. One of the typical mode (BW=3.75KHz) has been implemented in TSMC 180nm CMOS technology.