题目/Title：A 1.5–1.9GHz phase-locked loop (PLL) frequency synthesizer with AFC and Σ-Δ modulator for Sub-GHz wireless transceiver

作者/Author：靳宗明,俞小宝,韩思扬,宋颖,王自强,贾雯,池保勇
                        Zongming Jin,Xiaobao Yu,Siyang Han,Ying Song,Ziqiang Wang,Wen Jia,Baoyong Chi

会议/Conference：ICSICT 2014

地点/Location：Guilin, China

年份/Issue Date：2014.28-31 Oct.

页码/pages：pp. 1 - 3

摘要/Abstract：
A 1.5-1.9GHz phase-locked loop (PLL) frequency synthesizer with automatic frequency calibration (AFC) and third-order Σ-Δ modulator for Sub-GHz wireless transceiver is presented. A LC VCO ranging from 1.5GHz to 1.9GHze is integrated on this chip to meet multiple protocols. The voltage controlled oscillator is designed with modified digital controlled capacitor array to extend tuning range while minimizing the phase noise. An automatic frequency calibration (AFC) algorithm was implemented in this synthesizer to find the appropriate control word of the capacitor array. A 20-bit third-order Σ-Δ modulator is utilized to reduce out-of-band phase noise and to meet the frequency resolution of less than 30Hz as well as agile switching time.