Location：Home > Students > Past students
Zehong Zhang

Biography

Enrollment Date: 2011

Graduation Date：2014

Degree：M.S.

Defense Date：2014.05.27

Advisors：Baoyong Chi

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Research on Continuous-Time Sigma Delta Modulator for GNSS Receivers

Abstract:
In low-IF GNSS receivers, due to its high resolution, large dynamic range and intrinsic anti-alias characteristic, continuous-time Sigma Delta modulator could relax the requirements on the analog front-end, simplifying the architecture of the whole receivers. This thesis proposes two versions of continuous-time quadrature Sigma Delta modulator applied in low-IF GNSS receivers. The multi-mode reconfigurable modulator (v1) supports receiving frequencies including GPS L1, BD2 B1, GPS L2 and BD2 B2 with single channel. It could be switched between wide-band mode (20MHz) and narrow-band mode (5MHz). The wide-band modulator (v2) supports receiving most of the civil GNSS frequencies with dual channels. It covers 36MHz bandwidth. To meet the demand of flexibility, high speed and low power dissipation in multi-mode reconfigurable modulator (v1), this thesis proposes flexible opamp (FLOA), reconfigurable DAC and pre-amp. ELD compensation technique is adopted to enhance the stability of the loop. Low-latency DWA is presented to improve the linearization of the DAC, while introducing the least delay to the loop. Power scaling techniques such as “active-feedforward compensation” and “anti-pole splitted” are proposed to save power. What’s more, gate-leakage compensation technique is adopted to improve the performance of the DAC. To meet the demand of high-speed and high resolution in wide-band modulator (v2), this thesis proposes a 4th-order hybrid topology. ELD compensation is adopted with the feedback path moved to the input of the integrator, thus the adder is removed. To optimize the loop delay and enhance the stability of the loop, loop delay cancelled technique, high-speed and low-latency comparator, and DAC drived by C2MOS are proposed. Opamp with ac coupled driving stage is adopted to realize high linearization, high speed and high gain. Source degenerate resistance is introduced to suppress the noise of the DAC.

Publications

Papers：：

[1] Junfeng Zhang,Yang Xu,Zehong Zhang,Yichuang Sun,Zhihua Wang,Baoyong Chi, A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ΣΔ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver, IEEE Transactions on Microwave Theory and Techniques, Vol.65, No.4, pp. 1303 - 1314, 2017.

[2] Yang Xu,Zehong Zhang,Baoyong Chi,Nan Qi,Hualin Cai,Zhihua Wang, A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT ΔΣ ADC With AntiPole-Splitting Opamp and Digital I/Q Calibration, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.24, No.1, pp. 243 - 255, 2016.

[3] Junfeng Zhang,Zehong Zhang,Yang Xu,Baoyong Chi, A 54.4-mW 4th-order Quadrature Bandpass CT ΣΔ Modulator with 33-MHz BW and 10-bit ENOB for a GNSS receiver, RFIC 2015, 2015.

[4] Guodong Zhu,Junfeng Zhang,Yang Xu,Zehong Zhang,Baoyong Chi, A 1/2/4MHz multi-mode reconfigurable lowpass/complex bandpass CT ΣΔ modulator for short range wireless receiver, ASICON 2015, pp. 1 - 4, 2015.

[5] Yang Xu,Zehong Zhang,Baoyong Chi,Qiongbing Liu,Xinwang Zhang,Zhihua Wang, Dual-mode 10MHz BW 4.8/6.3mW reconfigurable lowpass/complex bandpass CT ΣΔ modulator with 65.8/74.2dB DR for a zero/low-IF SDR receiver, RFIC 2014, pp. 313 – 316, 2014.

[6] Xinwang Zhang,Yang Xu,Bingqiao Liu,Qian Yu,Siyang Han,Qiongbing Liu,Zehong Zhang,Yanqiang Gao,Zhihua Wang, Baoyong Chi, A 0.1-5GHz flexible SDR receiver in 65nm CMOS, A-SSCC 2014, pp. 249 - 252, 2014.

[7] Nan Qi,Zheng Song,Zehong Zhang,Yang Xu,Baoyong Chi,Zhihua Wang, A Multi-Mode Blocker-Tolerant GNSS Receiver with CT Sigma-Delta ADC in 65 nm CMOS, A-SSCC 2013, pp. 333 - 336, 2013.

[8] Zehong Zhang,Yang Xu,Nan Qi,Baoyong Chi, A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ Modulator with Digital I/Q Calibration for GNSS Receivers, A-SSCC 2013, pp. 393 - 396, 2013.