Biography

Enrollment Date: 2011

Graduation Date：2014

Degree：M.S.

Defense Date：2014.05.29

Advisors：Chun Zhang

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Critical Technology Research on Equalization Circuit in High Speed SerDes

Abstract:
With the increase of the transmission speed of high speed serial interface (SerDes), channel attenuation is serious. In this thesis, the technology of equalization is studied to compensate channel loss. Since equalization aims at channel loss, so channel is tested and analyzed firstly. And the problem of impedance matching should be solved since equalizer is at the terminals, so impedance matching technology is also studied. First, the transmission channel has been studied. A variety of transmission channels have been designed and measured to investigate the main factors that cause channel loss and impedance mismatch. Then PCB design are optimized to avoid these factors. The test results show that the channel attenuation and the signal reflection is not serious at 5GHz. So this channel can be applied to 10Gb/s SerDes. However, these problems are serious at 20GHz. More complicated equalization and impedance matching technology are required in 40Gb/s SerDes design. Then, the equalization technology study in 10Gb/s SerDes are introduced. An analog equalizer is designed in UMC 0.18um CMOS process. This circuit uses the combination of equalizer and inductive peaking circuit. The measured results verify the jitter decrease effect and bandwidth enhancement of the circuit. Then, the equalizer and impedance module in a source-synchronous transmitter is fabricated in SMIC 65nm CMOS process. The measured result shows that this circuit can compensate channel attenuation effectively. Third, an adaptive impedance matching module in Source-Series Terminated driver is designed and tested in SMIC 65nm CMOS process, the measured result shows that it can adaptively realize high precision impedance matching. The research on 10Gb/s equalizer is completed through the above works, and it lay the foundation of the following research on 40Gb/s equalizer. Finally, the key technologies on equalizer in 40Gb/s SerDes are studied. In this design, both equalizers cooperate with each other to equalize the channel. This design not only has high compensation ability, but also can adjust its equalization coefficients adaptively. And T-coil networks are used at the terminals to realize impendence matching and bandwidth enhancement. This circuit has been taped out and being tested.

Publications

Papers：：

[1] Naiwen Zhou,Linghan Wu,Ziqiang Wang,Zhihua Wang, A 28-Gb/s Transmitter with 3-tap FFE and T-coil Enhanced Terminal in 65-nm CMOS Technology, NEWCAS 2016, pp. 1 - 4, 2016.

[2] Linghan Wu,Shuai Yuan,Xuqiang Zheng,Ziqiang Wang,Chun Zhang,Zhihua Wang, A 10Gb/s source-synchronous transmitter in 65nm CMOS technology, EDSSC 2014, pp. 1 - 2, 2014.

[3] Linghan Wu,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Chun Zhang,Zhihua Wang, Co-design of 40Gb/s equalizers for wireline transceiver in 65nm CMOS technology, EDSSC 2014, pp. 1 - 2, 2014.

[4] Linghan Wu,Ziqiang Wang,Ke Huang,Shuai Yuan,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 10Gb/s analog equalizer in 0.18um CMOS, ASICON 2013, pp. 1 - 4, 2013.