Location：Home > Students > Past students
Xiaobao Yu

Biography

Enrollment Date: 2010

Graduation Date：2015

Degree：Ph.D.

Defense Date：2015.06.06

Advisors：Zhihua Wang Baoyong Chi

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：The Key Design Techniques of Dual-band Multi-mode Reconfiguable Trancesiver for Short Range Wireless Communicaiton

Abstract:
It has aroused great interests in the research of the transceiver (TRX) for short range wireless communication in ISM bands as the rapid development of wireless healthcare electronics, smart home, smart agriculture and son on. Different application scenarios feathers different data rates with all requiring low power consumption. This dissertation is about the key design technique of the dual-band multi-mode reconfigurable TRX for short range wireless communication, including the dual-band multi-mode architecture optimization, the filtering technique of the Out-of-Band (OB) blockers in receiver, the design technique of power amplifier with high output power and high efficiency, low power transceiver design techniques and the on-chip calibrations. The main contribution can be summarized as following: An architecture that features two individually optimized RF channel with a shared analog baseband is proposed to maintain the dual-band performance and the area overhead in this dissertation. A passive mixer clocked by 25%/50% duty cycle is utilized to achieve high linearity, low power consumption and OB blockers rejection. Several novel circuits are designed in the TRX, such as the balun LNA, the current reuse technique in the active balun with differential imbalance compensation, differential RSSI, and so on. This dissertation analyzes the effect on the receiver exerted from the out-of-band (OB) blockers. A blocker resilience technique based on the Q-enhanced LC tank is proposed in a receiver front-end which achieves 31dB filtering effect at the 130MHz offset. And the receiver can cope with a -15dBm blocker at PCS band. The OB filtering effect resulted from the 4-Path impedance translation is also utilized to attenuate the OB blocker. Furthermore, a complex baseband impedance is proposed in the 4-Path filter to settle the center frequency drift to adapt the low-IF architecture. An active notch filter combined with the 4-Path filter is proposed to reject the third order harmonics which archives a maximum 70dBc third order harmonic rejection，and a 12dB OB rejection at 20MHz offset. A multi-mode power amplifier (PA) with a dynamic load modulation network is proposed to enhance the average efficiency which is deteriorated by the PAPR induced by the complex modulation scheme, such as OFDM. The type matching network is analyzed and selected as the dynamic load modulation network. The design method of the multi-mode PA supporting PAPR is proposed in this dissertation with which the efficiency of PA in Sub-GHz band has been improved by ×1.41 and ×3.24 at 6dB and 9dB back-off powers, and by ×2.17 for the one in 2.4GHz band at 6dB back-off power. A low power transceiver design technique is proposed in this dissertation, including the TRX architecture optimization and low power circuits design, such as the frequency synthesizer based on Class-C VCO, the power scalable amplifier array technique in the channel filter and so on. The measurement result shows that a 5dBc improvement in phase noise at 1MHz offset has achieved with Class-C VCO compared with Class-A mode. A series of novel or improved calibration schemes to the offsets and mismatches due to the PVT variations has been proposed in this dissertation, such as the gain irrelevant DC offset calibration, current mode IQ mismatch calibration and the IIP2 calibration in the receiver part, and the LO leakage calibration and IQ mismatch calibration in the digital domain in the transmitter. Based on the architecture, method and technique addressed above, two chips for the short range wireless communications have been designed at last. The first chip targeting for the application defined by the 802.11ah is designed with a single-ended low noise amplifier to match the external antenna, a power amplifier, a 10bits ADC/DAC, a ∑-Δ fraction-N frequency synthesizer and a standard digital interface named JESD 207. Besides the function of the first chip, the second chip is capable of bearing a blocker with strength as high as -30dBm locating at 20MHz offset from the in-band signal. A series of calibration circuits have been designed to improve the robustness of the TRX.

Publications

Papers：：

[1] Xiaobao Yu,Meng Wei,Ying Song,Zhihua Wang,Baoyong Chi, A PAPR-Aware Dual-Mode Subgigahertz CMOS Power Amplifier for Short-Range Wireless Communication, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.63, No.1, pp. 44 - 48, 2016.

[2] Xiaobao Yu,Siyang Han,Zongming Jin,Zhihua Wang,Baoyong Chi, A Class-C VCO Based Σ-Δ Fraction-N Frequency Synthesizer with AFC for 802.11ah Applications, Journal of Semiconductors, Vol.36, No.9, 2015.

[3] Yun Yin,Xiaobao Yu,Zhihua Wang,Baoyong Chi, An efficiency-enhanced stacked 2.4-GHz CMOS power amplifier with mode switching scheme for WLAN applications, IEEE Transactions on Microwave Theory and Techniques, Vol.63, No.2, pp. 672 - 682, 2015.

[4] Xiaobao Yu,Meng Wei,Yun Yin,Ying Song,Siyang Han,Qiongbing Liu,Zongming Jin,Xiliang Liu,Zhihua Wang, Yichuang Sun, Baoyong Chi, A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS, IEEE Journal of Solid-State Circuits, Vol.50, No.11, pp. 2572 - 2590, 2015.

[5] Xiaobao Yu,Ying Song,Zhihua Wang,Baoyong Chi, Self-tuned SAW-less GNSS receiver front end with blocker filtering and gain-irrelevant DC offset cancellation, Electronics Letters, Vol.51, No.8, pp. 653 - 654, 2015.

[6] Haikun Jia,Baoyong Chi,Lixue Kuang,Xiaobao Yu,Lei Chen,Wei Zhu,Meng Wei,Zheng Song,Zhihua Wang, Research on CMOS Mm-Wave Circuits and Systems for Wireless Communications, China Communications, Vol.12, No.5, pp. 1 - 13, 2015.

[7] Xiaobao Yu,Meng Wei,Yun Yin,Baoyong Chi,Zhihua Wang, A Sub-GHz low-power transceiver with PAPR-tolerant power amplifier for 802.11ah applications, RFIC 2015, pp. 231 - 234, 2015.

[8] Bing Lyu,Yun Yin,Xiaobao Yu,Baoyong Chi, A 0.1-1.5G SDR Transmitter with Two-Stage Harmonic Rejection Power Mixer in 65-nm CMOS, ASICON 2015, pp. 1 - 4, 2015.

[9] Qiongbing Liu,Yu Xiaobao,Junfeng Zhang,Yang Xu,Baoyong Chi, A reconfigurable CBP/LP active RC filter with noise-shaping technique for wireless receivers, Journal of Semiconductors, Vol.35, No.9, pp. 095003-6, 2014.

[10] Lixue Kuang,Xiaobao Yu,Haikun Jia,Lei Chen,Wei Zhu,Meng Wei,Zheng Song,Zhihua Wang,Baoyong Chi, A fully-integrated 60-GHz 5-Gb/s QPSK transceiver with T/R switch in 65-nm CMOS, IEEE Transactions on Microwave Theory and Techniques, Vol.62, No.12, pp. 3131 - 3145, 2014.

[11] Ying Song,Xiaobao Yu,Zongming Jin,Baoyong Chi, A 49-dB DR wide locking range hybrid AGC for an ISM-band receiver in 0.18 μm CMOS, RFIT 2014, pp. 1 - 3, 2014.

[12] Zongming Jin,Xiaobao Yu,Siyang Han,Ying Song,Ziqiang Wang,Wen Jia,Baoyong Chi, A 1.5–1.9GHz phase-locked loop (PLL) frequency synthesizer with AFC and Σ-Δ modulator for Sub-GHz wireless transceiver, ICSICT 2014, pp. 1 - 3, 2014.

[13] Yun Yin,Baoyong Chi,Xiaobao Yu,Wen Jia,Zhihua Wang, An Efficiency-Enhanced 2.4GHz Stacked CMOS Power Amplifier with Mode Switching Scheme for WLAN Applications, CICC 2014, pp. 1 - 4, 2014.

[14] Xiaobao Yu,Meng Wei,Yun Yin,Ying Song,Siyang Han,Qiongbing Liu,Zongming Jin,Xiliang Liu,Zhihua Wang, Baoyong Chi, A fully-integrated reconfigurable dual-band transceiver for short range wireless communication in 180nm CMOS, A-SSCC 2014, pp. 257 - 260, 2014.

[15] Xiaobao Yu,Baoyong Chi,Meng Wei,A. Wang,Tianling Ren,Zhihua Wang, A half rate CDR with DCD cleaning up and quadrature clock calibration for 20Gbps 60GHz communication in 65nm CMOS, ISCAS 2013, pp. 962 - 965, 2013.

[16] Lixue Kuang,Baoyong Chi,Lei Chen,Meng Wei,Xiaobao Yu,Zhihua Wang, An Integrated 60GHz 5Gb/s QPSK Transmitter with On-Chip T/R Switch and Fully-Differential PLL Frequency Synthesizer in 65nm CMOS, A-SSCC 2013, pp. 413 - 416, 2013.

[17] Yang Xu,Baoyong Chi,Xiaobao Yu,Nan Qi,Partick Chiang,Zhihua Wang, Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver, IEEE Transactions on Circuits and Systems II-Express Briefs, Vol.59, No.1, pp. 30 - 34, 2012.

[18] Nan Qi,Yang Xu,Baoyong Chi,Yang Xu,Xiaobao Yu,Xing Zhang,Ni Xu,Patrick Chiang,Woogeun Rhee, Zhihua Wang, A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration, IEEE Transactions on Circuits and Systems -I: Regular papers, Vol.59, No.8, pp. 1720 - 1732, 2012.

[19] Nan Qi,Yang Xu,Baoyong Chi,Yang Xu,Xiaobao Yu,Xing Zhang,Zhihua Wang, A Dual-Channel GPS/Compass/Galileo/Glonass Reconfigurable GNSS Receiver in 65nm CMOS, CICC 2011, pp. 1 - 4, 2011.