Biography
Enrollment Date: 2010
Graduation Date：2013
Degree：M.S.
Defense Date：2013.05.28
Advisors：Zhiqiang Gao Albert Wang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Whole-chip ESD Protection Design Based on 0.35um BCD Process
Abstract:
This thesis is to explain the ESD phenomena in automobile electronic process and provide solutions to it. The process used here is ASMC’s 0.35um BCD technology, which includes Bipolar process, CMOS process and high voltage DMOS process. It is an urgent task to study how to provide high level of ESD protection for CMOS circuit and how to provide ESD protection for HV circuit, especially for the automobile chips which require an extremely high reliability. This thesis includes:Design and simulation of BCD technology for automobile electronics. This part introduces the features and applications of BCD technology, and derives the process flow and relevant parameters (such as dosage, energy, etc) from simulation with TCAD tools from Synopsys. With this process flow confirmed, further ESD design by simulation could be more accurate.ESD devices design under 3.3V CMOS process. This part focuses on the simulation of several ESD protection devices. With some improvements and innovative measurements, qualified devices within the design window are found for automobile electronic chips. With a triggering circuit constructed with two cascade diodes and the parasitic diode of the SCR, the DTSCR behaves perfectly as a power-clamp, which means the Vt1 and Vh are both a little higher than Vcc and also remains tunable. The PTD is a bi-directional device used for differential I/O in LF wakeup module of TPMS SoC, which works as ESD device tshows punch-through effect.Whole-chip ESD protection circuit design for Low-frequency wakeup circuit in TMPS SoC. A unique whole-chip ESD protection net is designed for specific chip module that can provide the chip with a viability of more than HBM 8kV ESD surge. LV PADs along with ESD devices designed earlier are designed according to the protection net to provide the specified ESD grade. These PADs are integrated into the LF wakeup module in TPMS, and a set of design flow for high grade ESD protection design is summarized. Co-design of ESD protection and EMI protection are discussed here, and an EMI filter with ESD protection is designed.HV ESD design based on SCR and HVNMOS. The main purpose is to solve the puzzle of HV ESD design window, provide the HV circuit with a whole-chip ESD protection scheme, a HV block with 6kV HBM ESD protection is verified, and the HV ESD design flow is summarized for further study:(a) Segmented SCR structure is used to increase Vh. TLP test showed a striking effect on Vh of the segment ratio, but accordingly the thermal breakdown current It2 is lowered. So a new layout is designed to increase the junction area to improve It2.(b) Floating active-area structure is raised to increase the Vh of SCR and dSCR. Both DC simulation and transient simulation showed a remarkably increase in Vh.(c) DSCR with punch-through effect is designed to provide ESD protection in the gate of HV MOSFET.(d) The double snapback effect of HVNMOS is discussed when it’s used for HV ESD protection, and the means to eliminate the effect is provided. The improved HVNMOS had a big increase in It2.