Biography
Enrollment Date: 2010
Graduation Date：2013
Degree：M.S.
Defense Date：2013.05.28
Advisors：Zhihua Wang Ziqiang Wang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research and Design for Transmitter Circuit of Muti-Channel High Speed SerDes
Abstract:
In rencent years, the techonolgy of computer and communication has been changing with each passing day. It has become an inevitable trend to achieve high data rate, low cost and low bit error rate, due to the demand of communication network data transmission being higher and higher. The performance of high speed data transmission is easily affected by the existence of clock jitter, clock skew and noise in the system. In order to ensure the good performance of the communication system, the serial communication interface with distinct advantages has emerged to replace the old parallel one which had been the mainstream interface technology in the past. This paper gives a brief description on the course of development and status quo of the serial communication, and carrys out a detailed research of the transmitter circuit of high speed multi-channel SerDes. The designed transmitter system consists of five data lines and one forward clock line. The data rate of each single data line is 9.6 Gbps, and it makes the total data rate up to 48Gbps. The key research contents of the paper are the transmitter circuit modules, including Mux circuit, transmitter equalization, terminal driver and impedance matching circuit.
The circuit is designed with 65nm CMOS process. Through simulation and chip test after taping out, the designed system functions properly, and the performance indicators also meet the pre-set target.