题目/Title：10Gbps串行接口发送端电路的设计
                        Circuit Design for Transmitter System of 10Gbps SerDes

作者/Author：马轩,王自强
                        Xuan Ma,Ziqiang Wang

期刊/Journal：微电子学与计算机 Microelectronics & Computer

年份/Issue Date：2013.19-23 May

卷（期）及页码/Volume（No.）&pages：

摘要/Abstract：
本文介绍了一个高速多通道SerDes发送端系统的设计。设计采用65nmCMOS工艺，单通道数据率为10Gbps。数据通道由一个全速率并串转换Mux电路和一个CML驱动器组成：在并串转换电路的高速部分，为了节省功耗和面积，采用TSPC型的锁存器和触发器代替CML型结构；输出驱动器采用CML结构，并加入一个四抽头的前馈均衡电路以减小数据信号码间串扰的影响；最后为了使信号能够无反射地进行传输，设计了阻抗匹配电路。
In this paper, a design for the transmitter system of muti-channel high speed SerDes is presented. It’s realized in 65nm CMOS process and the data rate of a single lane is 10Gbps.The data lane circuit consints of a full-rate MUX and a CML driver; The MUX is adopted the structure with TSPC latches and TSPC D-flip-flops (DFF) instead of CML circuits in the high speed stages to save power and area. The diver is made of CML structure, and a 4 tap feed-forward equalization (FFE) is applied in the driver to reduce the influence of ISI; Finally, the impedance matching circuit is used to avoid signal reflection in the channel.