Biography
Enrollment Date: 2009
Graduation Date：2012
Degree：M.S.
Defense Date：2012.05.28
Advisors：Zhiqiang Gao (Hong Chen Ming Liu)
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on Critical Circuits of Embedded SRAM IP Core
Abstract:
Embedded memory such as Static Random Access Memory (SRAM) plays an important role in the SoC system. The proportion of the memory area in the SoC system has reached over 85%. Memory IP core plays an increasingly important and decisive role on power, speed and integration of high-end SoC logic chips. However, high-end SRAM memory IP core based on advanced technology applied by Chinese chip design company is provided mainly by foreign IP provider. As a result, customized services and the product performance are severely constrained. Therefore, critical circuits in SRAM IP core based on the domestic advanced technology are studied and designed in this thesis. The results are helpful for Chinese SRAM IP core design and application with independent intellectual property. This thesis studies high-speed and low power design techniques in SRAM IP core. For high-speed SRAM IP core design, a common control circuit based on the RS latch is proposed to shorten the critical path and reduce the access time with good results. A timing control scheme based on replica bitline and self-timing is designed. This scheme can adjust the time by status register setting, and detect the precision of SRAM sense amplifier. The SRAM can work properly under the delay difference caused by process variation by post tape-out programming adjustment. Research on key technologies for high-speed SRAM design, this thesis also proposed a new divided bitline architecture, which substantially increases the SRAM access speed with a small area (1.3%) and power consumption (approx. 17%) penalty. The typical design of 512Kb SRAM IP in SMIC 65nm Low Leakage technology has been taped-out and tested. The test results show that the 512Kb SRAM IP with a divided bitline technology has the access time of 1.06ns at standard power voltage 1.2V. Compared to the same capacity SRAM IP without application of divided bitline, the access time has been decreased by 19.1%. For low-power technology research, according to the investigation of international advanced low-power SRAM design, this thesis designs the voltage down converter based on the resistor voltage divider principle, which is applied to the adjustable SRAM sleep voltage setting. Block-selection based SRAM power gating technology is designed using voltage down converter. Verified by simulation, depending on the sleep voltage setting, the SRAM array leakage power consumption is decreased by about 50%. In addition, as a SRAM IP, the thesis also verified the SRAM IP in an actual SoC system by tape-out, including the functional verification and the IP core file compatibility verification with back-end tools, to ensure the availability of the SRAM compiler and IP core.