Biography
Enrollment Date: 2009
Graduation Date：2012
Degree：M.S.
Defense Date：2012.05.28
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：The study on VCO-based-ADC which is used in Time-Interleaved Architectures
Abstract:
As the wireless communication technique is developing rapidly, a more critical specification is required for Analog to Digital Converters. Meanwhile as the Integrated Circuits fabrication technology advances to deep submicron domain, digital circuit design is becoming perfect day by day, this trend pushes Analog to Digital Converter to Radio Frequency band. Therefore converter which is able to process radio frequency signals and fulfill medium Effective Number Of Bits conversion becomes a new trend and direction.
This paper discusses a kind of time interleaved ADC which is able to realize high speed conversion first, summarizes the research status nowadays. The working principle, merits and drawbacks are introduced, certain non-idealities such as offset mismatch, gain mismatch and timing misalignment are analyzed, calibration methods are summarized, offset and gain mismatch calibration algorithms are researched and realized. Later the working principle of single channel architecture: VCO-based-ADC is illuminated. Key building blocks of such architecture: Sample and Hold Part, Voltage Controlled Oscillator and Frequency Quantizer are discussed from the designing perspective, the implementation type and simulation results of each building block are given. The sample and hold part adopts the basic sample and hold type, simulation results show that when the differential peak to peak 0.5V input signal is sampled by a 100MHz clock, the output resolution of S&H part is 9.7Bit; Voltage Controlled Oscillator employs a five stage ring oscillator, simulation results show the oscillator can reach maximum 3GHz tuning range using 0.18um technology, the nonlinearity is 0.78% in a 2GHz tuning range; Frequency Quantizer uses a fixed delay of 160ps delay line to generate a “Clock” whose maximum frequency is 6.25GHz, this “Clock” is used to identify the phase of VCO output, the overall output is the summing result of the identification output. Single channel circuit is simulated when a 37MHz, 0.5V differential peak to peak input is applied under 100MHz sampling clock, the total output resolution is 9Bit, ENOB is 6.03Bit and 5.12Bit after R+C+CC extraction.
An eight channel time interleaved ADC is implemented, each channel adopts a 100MHz clock whose duty cycle is one eighth. The overall sampling frequency is 800MHz, clock signal is generated from a Delay Locked Loop which has no clock jitter accumulation and has a stable duty cycle. Top layout design and tape out is under UMC 0.18um technology, problems which attention should be paid to and the limitations in the first edition are discussed. Finally the micrograph of the chip, PCB test board and a complete measurement scheme are given.