Biography

Enrollment Date: 2009

Graduation Date：2012

Degree：M.S.

Defense Date：2012.05.25

Advisors：Hong Chen

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Design of High-Speed and High-Stability SRAM Cell and Array

Abstract:
With the development of CMOS process, embedded SRAM is facing great challenges of leakage and stability. Speed is an important parameter of embedded SRAM. It is also the advantage of SRAM over other memories. How to control leakage and achieve high-speed, high stability is essential to embedded SRAM design. In this thesis, a deep study of design of embedded SRAM cell and array for high-speed and high-stability is presented. Further, built-in self-repair technology of embedded SRAM is also discussed. The main research work and results in this thesis are as follows:1. The impact of the development of CMOS process to embedded SRAM is analyzed. Especially, the speed, leakage, stability of SMIC 65/55nm low leakage process which is used in our design has been studied. The current research status and critical technologies of embedded SRAM are surveyed. And based on that, the difficulties in our embedded SRAM design are analyzed.2. The design and simulation methods of embedded SRAM cell are discussed. Several SRAM cells including standard 6T, asymmetric 6T, 7T, 8T were analyzed and designed. The application of multi-vt technology in SRAM design was analyzed. Besides, array division and interleaving bitline technologies used in SRAM array design are also researched.3. Thesis has analyzed the design methods of peripheral circuits which are suitable for SRAM compiler. The two-stage decoder and sense amplifier controlled by local timing was designed. They are configurable and meet the demand of SRAM compiler.4. The test and repair methods of the embedded SRAM were discussed. Through the analysis of SRAM fault models and test algorithms, the thesis proposed an effective built-in self-repair and built-in self-test strategy. The built-in self-repair strategy can solve the problem that the same faulty address may be saved more than once. 5. In this thesis, the technical schemes including array division, interleaving bitline, two-stage decoding and sense amplifier with local timing control were applied in a typical capacity of 16K x 32 bits SRAM. The SRAM chip was verified and taped out in SMIC 65nm CMOS process technology. The test results show that it can achieve 1.31ns access time. Besides, the built-in self-repair for a 4K x 32 bits SRAM has been designed and taped out in SMIC 55nm CMOS process technology. The post simulation results show it can work at up to 150MHz.

Publications

Papers：：

[1] Huamin Cao,Ming Liu,Hong Chen,Xiang Zheng,Cong Wang,Zhihua Wang, Design of High-Speed SRAM Array and Periphery for Compiler, Microelectronics, Vol.43, No.1, 2013.

[2] Cong Wang,Ming Liu,Hong Chen,Xiang Zheng,Huamin Cao,Zhiqiang Gao, Flexible Embedded SRAM IP Compiler Design Methodology Research and Implementation, Microelectronics, Vol.43, No.1, 2013.

[3] Cong Wang,Ming Liu,Hong Chen,Xiang Zheng,Huamin Cao,Zhiqiang Gao, An Embedded SRAM IP Compiler Design Methodology Independent of Technology and Circuit Structure, ICETCE 2012, pp. 246 - 249, 2012.

[4] Xiang Zheng,Ming Liu,Hong Chen,Huamin Cao,Cong Wang,Zhiqiang Gao, A 512 kb SRAM in 65nm CMOS with Divided Bitline and Novel Two-stage Sensing Technique, DDECS 2012, pp. 191 - 192, 2012.

[5] Huamin Cao,Ming Liu,Hong Chen,Xiang Zheng,Cong Wang,Zhihua Wang, Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable Redundancy, CECNet 2012, pp. 2565 - 2568, 2012.

Patents：

[1] Huamin Cao, Ming Liu, Hong Chen, Xiang Zheng, Cong Wang, Zhihua Wang, Zhiqiang Gao. A dual-port SRAM unit 6T structure with separate reading and writing: China, 201110282766.X[P]. 2013-12-04.

[2] Ming Liu, Hong Chen, Xiang Zheng, Huamin Cao, Zhiqiang Gao, Zhihua Wang. SRAM circuit device with divided bitline and two-stage sense amplifiers: China, 201110205980.5[P]. 2013-09-04.