Biography

Enrollment Date: 2008

Graduation Date：2011

Degree：M.S.

Defense Date：2011.05.26

Advisors：Woogeun Rhee

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Research on low cost, low power PLL clock generator

Abstract:
PLL (Phase-Locked Loop) based frequency synthesizer is a key building blocks both in wireless and wire-line communication system. As CMOS technology advances, SoC (System on Chip) standards require more critical specifications on chip area, power consumption, tuning range and spur of PLL. However, analog passive elements on chip become a bottleneck for scalability during low-cost PLL design process. Through study on low-cost, leakage-current immunity, PVT insensitive and wide-tuning range PLL design technique, this paper has achievement on quasi-type-I PLL design with focus on reference spur reduction. This paper presented the basic principle of  modulator and Fractional-N frequency synthesizer based on  modulator. The pros and cons of ADPLL (All-digital PLL) and Semi-digital PLL are review through recent publications. Meanwhile, the different functions of  modulator in different loop architectures are discussed. The reference spur issue is deeply proposed with its mechanistic and theoretical analysis. A Quasi-Type-I PLL technique is presented. We propose a voltage-mode frequency acquisition aid method which continuously tracks the frequency change and offers very fine digital resolution with modulation. Compared with ADPLL, it has better gain control over PVT variations, besides the all-digital PLL (ADPLL) suffers from the limited resolution and nonlinearity of the time-to digital converter (TDC) especially when advanced CMOS technology is not available. Compared with Type-I PLL, it reduces large reference spur or static phase error over wide frequency range. 38dBc reference spur reduction has been achieved compared with Type-I PLL in UMC 0.18m process. Besides, key building blocks design has been implemented in order to satisfy requirement of wide-tuning and low-power-consumption Quasi-Type-I PLL application. Wide-tuning range Current-Mode Logic divider is implemented in SMIC 130nm CMOS, which experimental results show that tuning-range is 2.74-to-5.37GHz. A semi-digital Automatic Amplitude Calibration PVT insensitive technique for trade-off between phase noise performance and power consumption over entire wide tuning range is presented. A prototype 0.36-to-1.13GHz ring VCO based Semi-digital PLL is implemented in advanced 65nm CMOS, while power consumption at 1.05-GHz is only 1.75mW.

Publications

Papers：：

[1] Yuanfeng Sun,Zhuo Zhang,Ni Xu,Min Wang,Woogeun Rhee,Tae-Young Oh,Zhihua Wang, A 1.75 mW 1.1 GHz Semi-Digital Fractional-N PLL With TDC-Less Hybrid Loop Control, IEEE Microwave and Wireless Components Letters, Vol.22, No.12, pp. 654 - 656, 2012.

[2] Yuanfeng Sun,Jun Li,Zhuo Zhang,Min Wang,Ni Xu,Hang Lv,Woogeun Rhee,Yongming Li,Zhihua Wang, A 2.74–5.37GHz boosted-gain type-I PLL with <15% loop filter area, RFIC 2012, pp. 181 - 184, 2012.

[3] Zhuo Zhang,Xican Chen,Woogeun Rhee,Zhihua Wang, A Cint-less type-II PLL with ΔΣ DAC based frequency acquisition and reduced quantization noise, A-SSCC 2012, pp. 301 - 304, 2012.

[4] Ni Xu,Zhuo Zhang,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, Technology-Friendly Phase-Locked Loops, MWSCAS 2011, pp. 1 - 4, 2011.

[5] Zhuo Zhang,Woogeun Rhee,Zhihua Wang, A Wide-Tuning Quasi-Type-I PLL with Voltage-Mode Frequency Acquisition Aid, ISCAS 2011, pp. 474 - 477, 2011.

[6] Zhuo Zhang,Jun Li,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, A Digitally Reconfigurable Auto Amplitude Calibration Method for Wide Tuning Range VCO Design, ICSICT 2010, pp. 542 - 544, 2010.