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Weitao Li

Biography

Enrollment Date: 2007

Graduation Date：2010

Degree：M.S.

Defense Date：2010.06.03

Advisors：Fule Li

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Study and Design of High Accuracy Pipelined A/D Converter

Abstract:
High accuracy pipelined ADC (analog-to-digital convertor) is used in high definition television system, high quality image system and communication system. Calibration techniques are needed for ADC with more than 10-bit accuracy to achieve high linearity and high dynamic range. In this paper, the principle of conventional pipelined ADC is reviewed. The non-ideal factors in ADC are described, and their effects are demonstrated by behaviorally simulation. A digital background calibration algorithm based on code occurrence count for pipelined ADC is proposed. This algorithm can calibrate conversion errors due to random capacitor mismatch, comparator offset, finite opamp gain, opamp noise and opamp offset. Without modifying pipelined stages, it can be implemented with small logic overhead and low switching activity. For A 14-bit pipelined ADC, the third harmonic is reduced from -32dB to -69 dB, and INL errors drop from 105LSB to 1.8 LSB. The linearity of the pipelined ADC is improved significantly. A 14-bit 50Msps pipelined ADC with PCEA (passive capacitor error-averaging) calibration technique is designed. The modified PCEA sampling network is used to reduce the load of the opamp. 1.5-bit/stage architecture is adopted to relax the requirement of the comparator. The SHA (sample-and-hold amplifier) is removed and the sampling networks are improved to decrease the aperture error. Gain boosted amplifier and Bootstrapped switch are employed. In the layout design, the critical signal path is optimized to reduce the parasitic capacitors. The post-layout simulation result shows the SFDR of the 14-bit 50MSPs ADC is 100dB. Occupying an area of 2.3mm×2mm with pads, the design is fabricated in 180nm mixed-signal CMOS technology.

Publications

Papers：：

[1] Hongyu Li,Fule Li,Weitao Li,Hanjun Jiang,Zhihua Wang, Design of a 5GS/s 200 MHz BW 74.8 dB SNDR continuous-time sigma delta modulator in 28nm CMOS, ISNE 2018, pp. 1 - 4, 2018.

[2] Xiuju He,Xian Gu,Weitao Li,Hanjun Jiang,Fule Li,Zhihua Wang, An 11-bit 200MS/s Subrange SAR ADC with Low-Cost Integrated Reference Buffer, Journal of Semiconductors, Vol.38, No.10, pp. 88-93, 2017.

[3] Jia Liu,Fule Li,Weitao Li,Hanjun Jiang,Zhihua Wang, A Flash ADC with low offset dynamic Comparators, EDSSC 2017, pp. 1 - 2, 2017.

[4] Weitao Li,Fule Li,Jia Liu,Hongyu Li,Zhihua Wang, A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator, A-SSCC 2017, pp. 225 - 228, 2017.

[5] Xuqiang Zheng,Fule Li,Zhijun Wang,Weitao Li,Wen Jia,Zhihua Wang,Shigang Yue, An S/H circuit with parasitics optimized for IF-sampling, Journal of Semiconductors, Vol.37, No.6, pp. 065005-1 - 5, 2016.

[6] Weitao Li,Fule Li,Changyi Yang,Minzeng Li,Zhihua Wang, A power-efficient reference buffer with wide swing for switched-capacitor ADC, Microelectronics Journal, Vol.46, No.5, pp. 410 - 414, 2015.

[7] Weitao Li,Fule Li,Changyi Yang,Shengjing Li, Zhihua Wang, A 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC, China Communications, Vol.12, No.5, pp. 14 - 21, 2015.

[8] Weitao Li,Fule Li,Changyi Yang,Shengjing Li,Zhihua Wang, An 85mW 14-bit 150MS/s pipelined ADC with a merged first and second MDAC, China Communications, Vol.12, No.5, pp. 14 - 21, 2015.

[9] Shengjing Li,Weitao Li,Fule Li,Zhihua Wang,Chun Zhang, A digital blind background calibration algorithm for pipelined ADC, NEWCAS 2015, pp. 1 - 4, 2015.

[10] Weitao Li,Fule Li,Ya Wang,Shengjing Li,Chun Zhang,Zhihua Wang, A power-efficient 14-bit 250MS/s pipelined ADC, NEWCAS 2015, pp. 1 - 4, 2015.

[11] Jifang Wu,Fule Li,Weitao Li,Chun Zhang,Zhihua Wang, A 14-bit 200MS/s low-power pipelined flash-SAR ADC, MWSCAS 2015, pp. 1 - 4, 2015.

[12] Meng Ni,Fule Li,Weitao Li,Chun Zhang,Zhihua Wang, A High-Speed analog front-end circuit used in a 12bit 1GSps Pipeline ADC, ASICON 2015, pp. 1 - 4, 2015.

[13] Jifang Wu,Fule Li,Weitao Li,Chun Zhang,Zhihua Wang, A 14b 200MHz power-efficient pipelined flash-SAR ADC, ICSICT 2014, pp. 1 - 3, 2014.

[14] Lingwei Zhang,Hanjun Jiang,Jianjun Wei,Jingjing Dong,Fule Li,Weitao Li,Jia Gao,Jianwei Cui,Baoyong Chi, Chun Zhang, Zhihua Wang, A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO, IEEE Journal of Solid-State Circuits, Vol.48, No.11, pp. 2705 - 2716, 2013.

[15] Weitao Li,Cao Sun,Fule Li,Zhihua Wang, A 14-bit Pipelined ADC with Digital Background Nonlinearity Calibration, ISCAS 2013, pp. 2448 - 2451, 2013.

[16] Changyi Yang,Weitao Li,Fule Li,Zhihua Wang, A Merged First and Second Stage for Low Power Pipelined ADC, ISCAS 2013, pp. 153 – 156, 2013.

[17] Changyi Yang,Fule Li,Weitao Li,Xuan Wang,Zhihua Wang, An 85mW 14-bit 150MS/s Pipelined ADC with 71.3dB Peak SNDR in 130nm CMOS, A-SSCC 2013, pp. 85 - 88, 2013.

[18] Jianjian Shao,Weitao Li,Cao Sun,Fule Li,Chun Zhang,Zhihua Wang, A digital background calibration algorithm of a pipeline ADC based on output code calculation, Chinese Journal of Semiconductors, Vol.33, No.11, pp. 115010-1-5, 2012.

[19] Cao Sun,Fule Li,Weitao Li,Hanjun Jiang, A configurable active-RC filter for half-duplex transceiver, ICSICT 2012, pp. 1 - 3, 2012.

[20] Lingwei Zhang,Hanjun Jiang,Jianjun Wei,Jingjing Dong,Weitao Li,Jia Gao,Jianwei Cui,Fule Li,Baoyong Chi, Chun Zhang, Zhihua Wang, A low-power reconfigurable multi-band sliding-IF transceiver for WBAN Hubs in 0.18μm CMOS, A-SSCC 2012, pp. 77 - 80, 2012.

[21] Shun Zhang,Weitao Li,Fule Li, A 400-440MHz Power Amplifier for Single-chip Wireless Transceiver, ITC-CSCC 2011, 2011.

[22] Weitao Li,Fule Li,Dandan Guo,Chun Zhang,Zhihua Wang, An Undersampling 14-bit Cyclic ADC with over 100-dB SFDR, Chinese Journal of Semiconductors, Vol.31, No.2, pp. 025008-1-6, 2010.

[23] Xiaobo Cai,Fule Li,Weitao Li,Chun Zhang,Zhihua Wang, A 12bit 100MSps Pipelined ADC without Calibration, CISP 2010, pp. 3547 - 3552, 2010.

[24] Weitao Li,Fule Li,Chun Zhang,Zhihua Wang, A Digital Background Calibration Algorithm Based on Code Occurrence Count for Pipelined ADCs, ICCCAS 2009, pp. 550 - 553, 2009.

[25] Weitao Li,Fule Li,Dandan Guo,Chun Zhang,Zhihua Wang, An Undersampling 14-bit Cyclic ADC, ASICON 2009, pp. 211 - 214, 2009.