General Description
The TLG32101 is a 12-bit analog-to-digital converter (ADC) optimized for high speed, high performance and low power. The circuit operates at up to a 270 MSPS conversion rate and presents outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including voltage reference, clock shaping, clock stabilizer, and LVDS drivers are included on the chip to provide a complete signal conversion solution.
The ADC requires a 1.2 V analog voltage supply and a 1.8 V digital voltage supply for the operation. A differential clock input is needed. The digital outputs are LVDS (ANSI-644) compatible and support offset binary format. A differential data clock output is available for proper output data timing.
Fabricated on SMIC 0.13um CMOS process, the TLG32101 is available in a 56-lead lead frame chip scale package, and is pin-to-pin compatible with AD9230 (ADI). The circuit’s performance is certificated by the third party testing at CESI, and is verified by the Alcatel-Shanghai Bell RRH60W feedback channel on system level.
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Figure1 Block diagram |
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Figure2 Micrograph |
Applications
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Features
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●Wireless and wired broadband communications
●Communications test equipment
●Power amplifier linearization
●Cable reverse path
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Highlights |
1. High Performance. Maintains 63.7 dB SNR @ 270 MSPS with a 120.1 MHz input.
2. Low Power. Consumes only 340 mW @ 270 MSPS.
3. SHA-less Front-end. Decrease power and noise contribution involved by traditional sample-and-hold amplifier.
4. Ease of Use. LVDS output and output clock signal allow interface to FPGA technology. The on-chip reference and clock shaping provide flexibility in system design. Standard serial port interface (SPI) supports various functions, such as clock duty cycle stabilizer and output test pattern switching.
5. Pin-to-pin compatible with ADI-AD9230.
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●SNR = 63.7 dB @ fIN up to 120.1 MHz @ 270 MSPS
= 64.7 dB @ fIN up to 120.1 MHz @ 200 MSPS
●ENOB of 10.2 @ fIN up to 120.1 MHz @ 270 MSPS
10.4 @ fIN up to 120.1 MHz @ 200 MSPS
●SFDR = −76.1 dBc @ fIN up to 120.1 MHz @ 270 MSPS (−1.0 dBFS)
●Linearity
DNL = ±0.3 LSB typical; 0.38 LSB peak
INL = ±0.5 LSB typical; 0.84 LSB peak
●LVDS at 270 MSPS (ANSI-644 levels)
●On-chip reference, no external decoupling required
●Low power dissipation
340 mW @ 270 MSPS (include LVDS drivers)
●1.2 V analog and 1.8 V digital supply
●Output data format: offset binary
●Integrated data capture clock
●Clock duty cycle stabilizer
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Publication
Xuan Wang, Changyi Yang, Xiaoxiao Zhao, Fule Li, Zhihua Wang, A 12-bit, 270MS/s Pipelined ADC with SHA-Eliminating Front End, IEEE ISCAS-2012, pp. 798 - 801.