Title：Reconfigurable convolutional neural network acceleration circuit based on asynchronous logic

Country：China

Patent No.：201810296728.1

Legal Status：Under review

Inventor：Hong Chen, Weijia Chen, Dengjie Wang

Assignee：Tsinghua University

Address：Tsinghua University,Haidian District Beijing 100084, China

Filing Date：2018-04-04

Issue Date：

The present invention provides a reconfigurable convolutional neural network acceleration circuit based on asynchronous logic. The circuit comprises three portions consisting of basic processing elements (PE), a processing array formed by the PEs and a configurable pooling unit. The circuit employs the basic configuration of a reconfigurable circuit to perform reconfiguration of the pressing arrayfor different convolutional neural network models; the circuit is integrally based on the asynchronous logic to employ a lock clock generated by Click units in an asynchronous circuit to replace a global clock in a synchronous circuit and employ an asynchronous pipeline architecture formed by cascading the Click units; and finally, the circuit employs the asynchronous communicating Mesh network to achieve data reuse to reduce power dissipation through reduction of the number of times of accessing the memory. The circuit provided by the invention is flexible and high in degree of parallelism and data reuse rate, and has a power consumption advantage compared to an acceleration circuit implemented through synchronous logic so as to greatly improve the processing speed of the convolutional neural network in the low power consumption. 

Patent Certificate： PDF/Jpg