Title：Power-aware power balancing S box unit circuit and application method thereof
Country：China
Patent No.：201110296995.7
Legal Status：Authorized
Inventor：Xiangyu Li, Feiyu Wang
Assignee：Tsinghua University
Address：Tsinghua University,Haidian District Beijing 100084, China
Filing Date：2011-09-30
Issue Date：2014-09-24
Abstract：
The invention discloses a power-aware power balancing S box unit circuit and an application method thereof, belonging to the technical field of power attack resistance. The power-aware power balancing S box unit circuit comprises an S box arithmetic logic module, a power-aware compensation logic module, a cycling shifter and a backcycling shifter, wherein the S box arithmetic logic module and the power-aware compensation logic module are simultaneously driven by an operand input port, and the S box arithmetic logic module calculates output values at a result output port and output values at a negative flag bit output port in accordance with input data; and the power-aware compensation logic module calculates output values at a compensation signal output port in accordance with the input data. The invention reduces the power consumption of power balancing, and provides the implementation of equivalent load balancing of multiple data lines in a random exchange interconnection line manner for the load balancing problem of the multiple data lines.
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