Biography
Enrollment Date: 2007
Graduation Date：2010
Degree：M.S.
Defense Date：2010.06.04
Advisors：Chun Zhang Xingjun Wu
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：A Design of Sub-threshold SRAM in 0.18um CMOS technology
Abstract:
Due to an extensive increase in the number of mobile and wireless applications the need for low power circuits is growing rapidly. The power dissipation in CMOS circuits can be decreased dramatically by lowering the supply voltage into the sub-threshold domain. However this makes the design of these circuits more challenging in terms of speed and robustness against for example noise. Realize based on a sub-threshold SRAM in a 0.18 um CMOS technology circuit design and layout have not been mentioned in each kind of literature. Circuit and layout design of a sub-threshold SRAM in a 0.18um has been studied in the paper, as well as the testing for chip. A 10 transistor cell of SRAM in the sub-threshold first been introduced, which is modified from classical 6 transistor cell. Due to the write operation only has small noise margin, the classical 6T cell in the sub-threshold domain is not likely to be successfully. Simultaneously introduced 10 units when the array is big, the leakage will possibly cause to read the operation failure. 11 Transistor cell has solved 10 unit leakage problems effectively, is the read and write operation reliable, may make a bigger array. But the area is bigger one time than classical 6T cell. In the paper has carried on the transistor size optimization design to 10T cell, additionally to the decoder, the input output circuit and so on has also made the speed, aspect and so on power consumption optimizations. Has completed a section of memory cell is 8X8 SRAM, and completes the circuit design, layout design and test for chip, obtained the lowest working voltage, the frequency, aspect and so on power consumption data, has provided the basis for afterward further research. Then based on 11T cell SRAM128X8 is built-in DW8051 digital circuit. This memory cell electric circuit was 11T cell which mentioned to front has made the improvement, used position on-line to pull the structure, raised the speed and the work stability. The chip domain aspect, has also made the improvement to the pad part, causes the test result to be closer the actual electric circuit the performance. Finally introduced in detail the DW8051 APR(Automatic Place and Route) design flow, provides the basis for the later sub-threshold value digital circuit auto place and route. Simultaneously introduced in passing the standard cell library domain design outlines, has been suitable for sub-threshold standard cell library design similarly.