Biography
Enrollment Date: 2006
Graduation Date：2011
Degree：M.S.
Defense Date：2011.12.16
Advisors：Chun Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：High-speed Interface Testing—The Realization of 40G Ethernet Simple Tester by FPGA
Abstract:
With the sustainable and rapid growth of 3G, VOD and high-definition television and other services, the market demand for the broadband is constantly challenging the limits of telecommunications infrastructure. After the related IEEE High-speed Ethernet rules were formulated, the equipment providers have displayed their 40G/100G products. As any other technology, the development of High-speed Ethernet devices need the test support, and also give a new request of the test system. As the technology development, FPGA has improved the processing bandwidth, there are more and more transceivers, it can realize the High-speed data rate and bandwidth requirements in a single devices, and became a carrier to realize the high-speed Ethernet design.
This paper presents a scheme for the realization of FPGA based 40G Ethernet tester. Firstly, it introduced the 40G Ethernet protocol and the key technologies of the 40G Ethernet tester realization, and then introduced a 40G high speed interface protocol -- Interlaken. Secondly, it introduced the hardware system of 40G Ethernet tester, the basic framework of FPGA design, and the function of each part. Thirdly, it stated the realization of 40G Ethernet tester design through the characteristics of FPGA, in which mainly described the process of Interlaken designs, including physical medium attachment sub layer ( PMA ), physical coding sub layer ( PCS ), media access control ( MAC ) and backpressure. Finally, it introduced the application framework and test results of 40G Ethernet tester.