Biography
Enrollment Date: 2006
Graduation Date：2009
Degree：M.S.
Defense Date：2009.12.21
Advisors：Chun Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Static Timing Analysis of TD-SCDMA Baseband Modem IC
Abstract:
The TD-SCDMA baseband modem IC HYP_ES1 is developed by Beijing T3G, based on China’s independent innovation of the third generation mobile communication standard, as the physical layer access. The baseband modem IC which is designed with CMOS065 technology features flexible interface and strong processing capabilities that compatible with many IC components. It interfaces to the GSM/GPRS/EDGE system solution from chipset vendors such as ST-Ericsson to support TD-SCDMA/GSM/GPRS/EDGE dual mode handset design. Static timing analysis belongs to the area of design verification. It is used to check whether the timing implementation of design can meet the timing requirement of design or not. The criterias which include operating condition, on-chip variation, signal integrity and the conditions of parasitic extraction should be considered for static timing analysis. In the IC HYP_ES1, two external pads are designed to bypass the internal PLLs in order to verify IC without PLLs. Before PLLs enter into stable status, all the internal clocks generated from PLLs are switched to the external clock input in order to implement power-up reset. In order to save dynamic power, the clocks which input to DSP can be divided by the fator which is configured by software registers. The duty cycle and sampling edge of the clocks for external interface can also be configured by software registers. There are a lot of clocks of which the relationship are very complexity. The external interfaces include radio frequency, system control, hardware debug and so on. Meanwhile it’s designed to support scan test, at-speed test, memory BIST, etc. It’s big challenge for static timing analysis of modem IC. It needs to define the analysis mode carefully, setup the analysis environment and constrain the timing correctly. After several rounds of static timing analysis, the IC HYP_ES1 has been tape-out sucessfully. After silicon validation, all the timing requirements are met.