Biography
Enrollment Date: 2006
Graduation Date：2009
Degree：M.S.
Defense Date：2009.12.21
Advisors：Chun Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Back-End Design of the Multi-Power Domain Multi-Clock Domain ASIC CV8000
Abstract:
The purpose of the thesis is to solve the low-power back-end design issue in deep sub-micron process, implement the complex clock tree structure and ensure the performance of the chip. It presents a series of design methods and achieves the design and validation. First, a multi-power domain is applied to solve the static leakage power problem which is introduced by the deep sub-micron process. The power domain partition, floorplan and isolation are reviewed and researched, as well as the EM and IR-Drop issues. Then a simplified mathematical model is extracted to implement the initial design of the power supply network. The power supply network also gets analyzed and optimized by EDA tools to achieve the best network design with multi-power domain. By studying the clock tree theory and the clock structure of the chip, a process is implemented, including physical synthesis, clock tree design, clock tree synthesis and clock tree analysis. With adoption of multi-level clock tree synthesis strategy, Useful-Skew idea and the final optimization, the timing before and after the clock tree synthesis becomes consistent. Finally, the routing strategy and solution of cross-talk issues are discussed based on EDA tools. The chip’s performance is verified under the most pessimistic conditions. After Sign-off verification, the chip has been successful tapeout. After testing, all the design requirements have been achieved. The internal CPU frequency achieves more than 333MHz; the power consumption is less than 0.5mW in power-saving mode.