Biography
Enrollment Date: 2006
Graduation Date：2009
Degree：M.S.
Defense Date：2008.12.18
Advisors：Chun Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design of UHF RFID Reader Baseband Processor
Abstract:
Due to its advantages in information management automation, RFID technology has been endowed considerable attention and has been developing rapidly for the recent years. However, there has been little research on UHF RFID readers; moreover, such readers have a variety of drawbacks, ranging from large power consumption, poor performance and high cost to clumsy volume and lack of portability. Nevertheless, with the progress of SOC design technology, RFID readers with low power consumption and high performance became possible, of which single-chip integrated reader design has been gaining the attention of RFID researchers. This paper discusses the baseband design of a RFID reader.
The basic principles and frame of RFID are introduced firstly in this thesis. The system design of RFID reader is given,and both the frame and corresponding principles of each module are elaborated,then the function and structure of baseband processor are introduced. The protocol standards of ISO/IEC 18000-6C are introduced in the thesis.
A baseband processor of UHF RFID reader based on ISO/IEC 18000-6C is implemented in this thesis.Considering characteristics of single-chip reader,this thsis choosed Actel company’s AFS600 as system platform,and built framework of baseband processor of reader using the DW8051 MacroCell and embedded Flash of AFS600.According to this platform,a on-chip debugging system is expanded for the DW8051 MacroCell,which originally did not support debugging mode,then a Dynamic Linkable Library and a downloader is developed to support this on-chip debugging system.Finally,many debugging functions is realized in Integrated Develop Environment Keil,including compile,simulation,download and on-line debug.Based on ISO/IEC 18000-6C protocol and this debugging enable microprocessor, the hardware implementation of pathway of transmitting and receiving is given in detail.This pathway is verified correctly on AFS600 platform,after function simulation,synthesis,place&route and post-layout simulation.