Biography
Enrollment Date: 2006
Graduation Date：2009
Degree：M.S.
Defense Date：2009.06.02
Advisors：Chun Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Implementation of XTEA on UHF RFID chip
Abstract:
RFID is used to identify items by using long-range radio frequency communications. It can be used to track and manage virtually all physical objects.During the last decade, with the rapid processing of CMOS technology, Radio Frequency Identification (RFID) system is applied in more and more areas, such as supply-chain management, inventory control, automobile manufacturing, etc. However, the broadened application of RF tags brings latent security and privacy risks. There are two kinds of risks during communication. One is the eavesdropping into radio communications and replaying the data. The other is the invalid access to purloin information from either the transponder or the transceiver. Thus authentication and data encrypting is pivotal for security of a RFID system. This paper analyzes the existing RFID system oriented security protocols. Based on conventional mutual symmetrical authentication, implement of the security scheme in a RFID tag is described in this paper. The security scheme is embedded in a practical RFID standard, which is established based on the ISO/IEC18000-6C draft of American National Standard. The practical RFID standard is analyzed in detail in this paper. State machine design, memory design and interface design of the RFID tag’s digital logic part is given. XTEA algorithm is selected as the main encryption algorithm in this paper. While carrying out the XTEA algorithm, trade-off between processing speed and area spending has been done in this paper. Software design of a RFID reader is elaborated in detail and the algorithm of the processing is explained in the paper. In the basis of this, software design of security and privacy is finished. A tag simulator is designed to simulate the function of a tag. It is very important for design and debugging of the reador. The integrated design of the tag is fabricated in a 163.2μm x 163.2μm die, using UMC 0.18μm 1P6M CMOS technology, containing 2766.8gates. Under a 250kHz system clock, it takes 5ms to complete the whole authentication process.