Biography
Enrollment Date: 2006
Graduation Date：2009
Degree：M.S.
Defense Date：2009.05.31
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design of pipelined ADC basing on code density statistics calibration
Abstract:
High-speed, high-precision ADCs are wildly used in many fields. Among multiple structures of ADCs, pipelined ADCs have great development potential because of the compromise between speed and precision. However, different kinds of non-ideal factors will be introduced into pipelined ADCs during design and manufacture processes, such as finite Opamp gain and capacitor mismatch, so the precision of traditional pipelined ADCs is hard to improve further. One of the solutions is the introduction of calibration process. The function of calibration process is to measure the error of the system and adjust the digital output according to the measured errors, so as to improve the precision of pipelined ADCs. This thesis proposes a new digital background calibration technique for pipelined ADCs .The real weight of each digital bit can be recalculated by making statistics of occurrence frequency of the output codes from comparator and backend ADC. Multiple errors from different error sources, such as finite Opamp gain and capacitor mismatch can be calibrated with the recalculated real weight. Behavioral simulation results with MATLAB show the proposed calibration technique can calibrate 40dB finite Opamp gain and 10% capacitor mismatch to reach an ENOB of 13 bits. Basing on the behavioral simulation results, the thesis finishes the circuit and layout design scheme of a 13-bit 50MS/s pipelined ADC with the proposed calibration technique. The layout was fabricated in UMC 0.18um 1P6M standard CMOS process. The post-simulation results show with 50MHz sampling rate and 23.5MHz input signal, the proposed calibration technique increases SFDR from 57.6dB to 78.9dB, SNDR from 60.2dB to 88.7dB and ENOB from 9.2bits to 12.8bits.