Biography
Enrollment Date: 2005
Graduation Date：2008
Degree：M.S.
Defense Date：2008.12.19
Advisors：Fule Li Chun Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design of Low Power High Accuracy Pipeline A/D Converter
Abstract:
The analog-to-digital converter is one of the most important modules in the design of high integrated and high speed SOC. The pipeline analog-to-digital converter (ADC) is widely used in video and high-speed imaging, because pipeline architecture can provide a good trade off among the resolution, speed and power consumption. This thesis mainly focuses on the low power and high accuracy techniques in pipeline ADCs, and finally uses 3 different ADCs to verify these techniques. First, all kinds of error sources, such as sampling switch non-linearity, operational amplifier finite DC gain, capacitor mismatch and comparator offset, are analyzed in detail. And correspondingly, the remedies are proposed. Second, low power techniques such as the front-end sample-and-hold amplifier (SHA) cancellation, opamp sharing, scaling down and high accuracy techniques such as passive capacitor error averaging (PCEA), bootstrapped switch, high gain opamp, are all analyzed circumstantially. In this part, two new ideas are proposed: ① after the cancellation of the front-end SHA, the sampling circuit in the first pipeline stage is modified to reduce the frequency limitation of the input signal; ② based on the conventional PCEA technique, the sampling circuits in the pipeline stages (except the first stage) are modified to reduce the power consumption. Third, according to the low power and high accuracy techniques above, this thesis realized a 13-bit 8MSample/s pipeline ADC. The measured results show that it achieves 12-bit ENOB (effect number of bits) and consumes 56.7mW at 8-MHz sampling rate. Correspondingly, the FOM value is 1.7pJ, which gets the design goal. Fourth, according to the low power and high accuracy techniques above, this thesis realized a 14-bit 1MSample/s cyclic ADC, which used two pipeline stages. According to the measured results, the peak SFDR is 87.5dB, 86.1dB and 75.4dB at 357KSample/s, 714KSample/s and 1.14MSample/s, respectively, which also achieved the design goal. Finally, according to the low power and high accuracy techniques above, this thesis realized a 14-bit 10MSample/s pipeline ADC. According to the measured results, the ADC was modified. The post-simulation results show that the peak SFDR is 95.8dB and the ENOB is 13.5-bit at 10MSample/s.