Biography
Enrollment Date: 2015
Graduation Date：2018
Degree：M.S.
Defense Date：2018.05.25
Advisors：Zhihua Wang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Digital implementation of on-chip spike sorting algorithm in deep brain neural signal acquisition
Abstract:
The brain-computer interface is a new type of connection between the brain and
the external device. It can replace or repair damaged nerves. It has extremely broad
application prospects in fields such as health care, smart home, game entertainment,
biometrics, and educational technology.
The neural signal processing unit can analyze and process the recorded raw neural
signals, give intuitive or qualitative classification results of the subjects’ intentions, and
configure the neural stimulation pattern accordingly as feedbacks to implement a real-time
closed-loop control, which is quite essential for applications that need spontaneous feedbacks. Besides, with the development of high-density multi-electrode arrays, thousands
of channels can be recorded at the same time, which poses great challenge to wireless
data transmission, resulting in high power consumption and high data loss. An effective
solution to this problem is the on-chip neural signal processing unit.
This thesis reviews existing Neural Signal Processing methods and evaluates these
algorithms. On the premise of ensuring spike detection and classification accuracy, taking
into account the compromise between hardware consumption and classification latency. A
hardware architecture including spike detection, feature extraction and classification was
implemented. And completed the control module for neural stimulator in brain-machine
interface closed-loop control.
This thesis adopts a double-threshold-based spike detection method to realize a spike
detection circuit with low hardware cost and high detection accuracy. Using the extremum
method of the first derivative and the second derivative of the spike waveform to extract
the characteristics of the spike, a feature extraction module with simple hardware and
high data compression rate is realized. The support vector machine algorithm is used
to implement the spike classification. The classifier uses a two-stage pipeline to timedivision multiplex the adder and multiplier in the algorithm, which can effectively reduce
the hardware cost. And through the way of reuse, three categories can be achieved.
Moreover, the classification accuracy rate of this algorithm is still above 90% when the
signal SNR is low. The architecture is implemented using the TSMC 0.18um HV process
with a circuit area of 1.1×1.7mm2. In addition, the control module of the neural stimulator
is completed, and the configuration of the pulse parameters of the 8-channel stimulator was realized, and the closed-loop control scheme of the stimulator based on the classification
result of the neural signal processing module is discussed.