Biography
Enrollment Date: 2005
Graduation Date：2008
Degree：M.S.
Defense Date：2008.06.06
Advisors：Zhihua Wang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on Single-loop Multi-bit ΣΔ ADC Technology
Abstract:
ΣΔ ADC has been widely used because of its high resolution and high integration density within digital systems. In the last decade, high performance ΣΔ ADCs with low power and high speed have been deeply researched. Many new circuit topologies have been designed for special applications, among which the multi-bit quantization technique is often used. This thesis focuses on the key design technique of the multi-bit ΣΔ ADC. Based on the analysis of the principle of ΣΔ ADC, this thesis summarized the advantages of multi-bit ΣΔ modulator and analyzed the problems in the design. Firstly from the aspect of system design, the thesis analyzed the modulator coefficients' influence on the whole performance, and found out a set of solution with good stability through parameter sweep methodology. Then the DAC nonlinearity issue of multi-bit ΣΔ ADC was introduced and dynamic element technique (DEM) was discussed to solve this problem. In order to simulate large scale mixed-signal system quickly and effectively, this work established a new library module using DEM technique inside the current version of Matlab SD Toolbox, and studied on the behavioral-level simulation of the modulator by analyzing the non-ideal factors in real circuits. This work designed a single-loop 3-order 4-bit ΣΔ modulator. The signal bandwidth is 22.05KHz and the target resolution of the ADC is 16-bit. The chip was fabricated in UMC 0.18um standard CMOS process and was tested in the following step. The 1M-point noise base test showed that the average noise power spectrum density is under -140dB, indicating a 96.9dB SNR and 15.9-bit ENOB. Single-end sine wave coarse test showed that the modulator achieved at least 75.2dB SNDR, 90.6dB SFDR and 12.2-bit ENOB. The measurement results approved the correctness of the design.