Biography
Enrollment Date: 2014
Graduation Date：2017
Degree：M.S.
Defense Date：2017.05.24
Advisors：Hong Chen
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design Method Research On Asynchronous Circuits
Abstract:
As the continuous development and scaling-down of intergrated circuits, the problem of power in intergrated circuits is more serious than ever. To save energy,researchers are using many methods of harvesting power from other materials. This paper set up a method on asynchronous circuits design to solve this problem. Significant handshake protocol of asynchronous circuits is introduced after the submission of the principle and recent status of research. Basic modules of C element and Click element are described and requirements of them are elaborated in this paper. Eventually, simulation and verification in FPGA are performed. Characteristics and functions of Muller pipeline are analized and an asynchronous GFSK demodulator is designed on basis of C element and Muller pipeline. Principles of this GFSK demodulator are introduced. Design and implementation is given. Then simulation and timing verification is performed and passed. The synthesis tool shows that asynchronous GFSK demodulator occupies 5758 um2 of area and consumes 5.50 uW of power. Compared with the synchronous GFSK demodulator, the asynchronous one reduces 21% power consumption and 29.1% area occupation. This asynchronous demodulator can bear ±70KHz shake of frequency and ±1V DC offset. Any angle of phase offset is available. The Eb/N0 of 1% bit-error rate is 10.95dB.
An asynchronous loop structure is introduced in this paper and could be used in Micro-Control Unit (MCU). Compared with pipeline structure, this loop structure uses single control unit in stead of cascade units to save area. An asynchronous accumulator is designed to verificate the function of the loop structure. After simulation and verification on FPGA, the results show that this accumulator could be precisely controlled and meet the requirement of asynchronous handshake protocol. This asynchronous loop structure could be adopted in the entire control path in MCU and other circuits.
Asynchronous branch nested loop structure is introduced, designed and
implemented based on this asynchronous loop structure. An asynchronous MCU control path is designed and implemented using this complex structure. Cadence Virtuoso and Altera Quartus II software are used in this paper to perform pre-simulation and post-simulation. The imulations are passed. Moreover, post-simulation performs additional PEX delay from pre-simulation. Layout is made by Cadence Virtuoso based
on UMC 0.18um technology. The circuits will be taped out in UMC 0.18um technology. Testing program is given and PCB design is produced at the end of this paper.