Biography
Enrollment Date: 2013
Graduation Date：2017
Degree：M.S.
Defense Date：2017.01.14
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：A Double Mode Histogram-based Background Calibration for Pipelined Analog-to-Digital Converter
Abstract:
High speed high resolution pipelined ADC are widely used in wire-less communication, medical imaging and base station. The development of these systems also drives the pipelined ADC towards higer resolution, higher speed and lower power. However, as the further developing of the manufacturing technology, it becomes more difficult to improve the performance of pipelined ADC which depend on high gain opamp (operational-amplifier) and well matched capacitors. These non-ideal factors limit the performance of pipelined ADC, thus it is important to apply calibration technology in ADC in the actual industrial production.
Among all traditional calibration methods, the histogram-based digital calibration has great advantages, it introduces only simple modification into the analog circuit and requires no specific test signals. However, since the histogram-based calibration technique extracts error information from the distribution of the output codes, the performance of traditional histogram-based calibration techniques may depend on the statistics of the input signal. In order to solve this problem, a new histogram-based calibration technique is proposed in this paper.
In the proposed histogram-based calibration technique, two switching modes are applied, the effect of input signal distribution on the performance of the technique and the circuit implementation are analyzed in details. Since the proposed technique extracts error information from the same input range with two modes switching with each other and the histogram of one mode acts as the reference of the other, the technique is much less sensitive to the input statistics. What’s more, the implementation of two modes only introduces simple modifications into the circuit, which greatly reduces the complexity of the technique.
In order to evaluate the performance of the technique, a pipelined ADC with two modes is designed in circuit level by making only simple modifications. Since the background calibration needs a lot of samples, an interception model is built and the verification is made based on it. The simulation shows that the performance of ADC is greatly improved after the calibration, ENOB improves from 11.5-bit to 12.4-bit, SNDR improves from 71dB to 76.5dB, SFDR improves from 81.4dB to 90dB. In order to verify that the proposed calibration technique is not sensitivity to input signal statistics, an AM signal is provided. The calibration result is almost the same as other input signals. Besides, some factors such as the parameters of the algorithm, the distribution and amplitude of the input signals are also analyzed. The results show that the proposed technique works well in different situations and is much less sensitive to the input statistics.