Biography
Enrollment Date: 2013
Graduation Date：2016
Degree：M.S.
Defense Date：2016.06.01
Advisors：Liji Wu
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research and Design of Power Management Circuit and Voltage Detecting Front-End for BMS Chip in New Energy Vehicles
Abstract:
In order to deal with the increasingly serious environmental and resource restraints, our country has concentrated on new energy vehicles. Design of battery management system and it’s key chip is one of the key supporting technologies for new energy vehicles. Battery management chip can detect voltage of battery packs , can be stacked to expand the supported numbers, and make it possible for the management and balance of large-scale battery arrays. Study in this field is urgently needed for our country.In this paper, application environment and functional requirements of battery management chip was explored. Two key modules of power management circuits on chip and battery voltage acquisition front-end (MUX + ADC) was designed under the ASMC 0.5um 60V BCD process. Content of the work will be described later.A wide input voltage power management circuit has been implemented. Power supply rejection ration of reference circuit was greatly improved with the combination of pre-regulator and negative feedback loop. A simple smooth hando? soft-start circuit is designed to ensure safety during. The circuit is able to deliver current from zero to 20mA with good stability, the input voltage is 5.5V 40V and output voltage 5VNext is the design of high voltage (HV) analog multiplexer (MUX) circuit with voltage inputs of eight series connected battery cells. The main part of HV MUX is several parallel connected HV switches. A HV switch is composed of complementary DMOS devices and gate drive circuit, and has eliminated the error in the signal path caused by quiescent current. The MUX circuit drives a wide common mode range di?erential voltage detecting circuit. Elimination of level shifter circuit causes reduction in power consumption, and greatly improves the detecting accuracy. The simulation results show that, operating current of MUX circuit is 30uA, error introduced by the HV MUX circuit without calibration is less than 0.2mV.Finally, a design of second order incremental Simga Delta ADC is presented. Using of tools such as Simulink and Verilog-A helps determining the modulator structure select and verification. Detail analysis and modeling of the non-ideal properties of the circuit, provides a reliable guidance for specific circuit design. The core circuit works under low voltage domain is able to detect the high voltage, wide common mode, unipolar input signal with the help of level shift and voltage isolation design. Simulation result shows that modulator has ENOB greater than 16Bit, operating current 100u with 256 times over-sampling ratio. Multi-channel detecting error of battery voltage is less than 0.3mV. I have finished the front-end and physical design for all modules above and am waiting for tape out process, which has completed the mask jobview, photolithographic, and is running online process.