Biography
Enrollment Date: 2013
Graduation Date：2016
Degree：M.S.
Defense Date：2016.05.30
Advisors：Hu He Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design of a Hybrid Branch Predictor on a Hybrid Microprocessor
Abstract:
Digital Signal Processor (DSP) has been widely applied in the fields of communications, radar, multimedia processing, for its good signal processing performance. With the constant development of computer technology, people’s requirements for processor performance are also getting higher and higher. Fully improving instruction-level parallelism (ILP) to improve processor performance has become an important topic. Superscalar and very long instruction word are two structures designed to improve the quality of parallelism designed, due to the different stages to improve instruction parallelism, both of which have advantages and disadvantages. Orchid is a general-purpose DSP running ARM instruction set, which has both the advantages of processing performance of DSP and generality of ARM. Orchid uses a mixed architecture of Superscalar-VLIW, and a ten-stage pipeline structure.Based on the development of Orchid, this paper designs branch prediction on Orchid, aiming to fully improve processor performance. Since Orchid has a deep pipeline, if Orchid does not have branch prediction, when branch instruction jumps it will flush the pipeline, wait for the target instruction to pass along the pipeline to the execution stage, and then execute. As a number of instructions execute in parallel per week, branch instructions bring a huge performance loss. So a accurate design of branch prediction structure can sufficiently reduce such losses, improving processor performance.Branch prediction structure of the subject uses a bimodal-PAp mixed prediction mechanism. Bimodal prediction is used for unconditional branch instructions, to reduce the hardware area, reduce training time and improve prediction stability. PAp prediction is used for conditional branch instructions, to fully improve prediction accuracy. To fit the hardware architecture of Orchid, the design takes a number of measures, compared with traditional branch prediction, to reduce training time, improve prediction accuracy and efficiency. The branch prediction on Orchid can make predictions in both modes of Superscalar and VLIW, fully improving the performance of processor.DSPstone, Dhrystone and EEMBC standard programs are run on Orchid to test the performance of branch prediction structure, and xilinx vivado synthesis tools are used for FPGA verification. The test results show that the bimodal-PAp hybrid predictor has higher prediction accuracy compared with single bimodal predictor, and significant performance improvement, with an average increase performance of more than 30%. Meanwhile in the overall processor core hardware resources, the branch prediction structure takes only a small part. using hybrid predictor can effectively reduce the hardware logic resource usage and hardware area.