Biography
Enrollment Date: 2013
Graduation Date：2016
Degree：M.S.
Defense Date：2016.05.30
Advisors：Woogeun Rhee
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：F/PLL Based Clock Generator Design
Abstract:
Through the research of phase-locked loop (PLL) based clock generation circuits, a PLL architecture which achieves a low noise and spur performance with low reference frequency is proposed. Then, a method of improving the phase noise performance for
the PLL with a binary phase detector or the bang-band PLL (BBPLL) is proposed, which can be useful for spread-spectrum clock generation (SSCG) applications.
This thesis first describes a hybrid frequency/phase-locked loop (F/PLL) in which
a PLL operates as a nested digitally-controlled oscillator (DCO). The nested DCO based
on the wideband PLL not only offers a constant gain but also enables low noise clock
generation even with a very low reference frequency. A digital FLL with a 1-bit
frequency detector (FD) is designed as a main loop to avoid the complex linear
time-to-digital converter (TDC) design. Detailed system architecture and circuit design
are shown and a prototype fractional-N F/PLL is implemented in 65nm CMOS. The
proposed F/PLL achieves an in-band noise of -90dBc/Hz at 1.5GHz output with a
15kHz reference clock and a 60MHz system clock, consuming 9.2mW from a 1V
supply.
The thesis then describes the improvement of the output phase noise of the BBPLL
by utilizing a finite impulse response filtering and delay compensation methods to
minimize the input dynamic range of the bang-bang phase detector (BBPD). Detailed
system analysis is done, and circuit designs are shown. The BBPLL is designed to
operate at 800MHz with the input reference frequency of 30MHz. By implementing an
8-tap FIR filter and a 5-bit delay chains, behavioral simulation results show that the
proposed methods improves the phase noise of BBPLL by more than 20dB. The SSCG
based on the BBPLL is implemented with 65nm CMOS technology.