Biography

Enrollment Date: 2013

Graduation Date：2016

Degree：M.S.

Defense Date：2016.05.30

Advisors：Ziqiang Wang

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Critical Technology Research on Transmitter in 40Gb/s High Speed SerDes

Abstract:
With the development of modern high-speed Internet technology, the information industry based on Cloud Computing and Multi-core processing technology, such as Internet of Things, Big Data, have been developing rapidly. The stronger the ability of "computing" grows, the faster the speed of the "data" interaction will be. Against this background, the High-Speed Serial Link technology is becoming another highlands of modern information technology. As one of the most important high-speed data transmission technology, High-Speed Serial Link technology (SerDes) is becoming a research hot in academic and engineering field in recent years. IBM has developed a 28Gb/s Serdes commercial products, and the 40Gb / s or 56Gb / s Serdes is coming through on the way. This paper focus on the study of transmitter (TX) of 40Gb/s SerDes. solving channel attenuation of signals at high frequency, achieving high-speed MUX, and avoiding the mismatch between the clock and data in every stage MUX are the three biggest challenges in the designing high speed TX. Firstly, a 3-Tap FFE based on LC network as the delay cell, working in 40Gbps for high-speed serial circuit, is proposed. A closed loop feedback circuit is designed to control value of the voltage-controlled-capacitance, which is used to achieve one UI precise delay. The proposed FFE can solve the tighten timing issue due to the use of timing circuit as a delay cell in traditional FFE circuit. Secondly, a 64-1 MUX circuit is introduced, which is used to serialize 64 low-speed parallel data to 1 high-speed seral data. The six cascading MUX is divided into two parts, the 64-4 MUX as low-speed part and the 4-1MUX as high-speed part. The TSMC65 library elements,such as DFF and NAND, are used to design circuit in low-speed part. A variety of inductor peaking technology is used to expand the bandwidth of the circuit in the high-speed part. Furthermore, the clock distribution circuit of TX is designed to provide clock signal for sampling in every stage MUX. As previously described, the data signal from 6 stages cascading MUX, which serialize the 64b parallel 625 Mb/s data to 1b serial 40 Gb/s data. While the clock signal is generated by frequency divider chain, which divides the 20GHz differential clock into various frequencies by 5 stages cascading dividers. The direction of data chain and clock chain is reverse, which results in the mismatch in one or more stage MUX. In order to solve this problem, this paper proposes a timing loop feedback circuit to regulate data and clock to ensure that sampling is right in every stage MUX. Finally, the designed 64-1 TX is verified by simulation and experiment results

Publications

Papers：：

[1] Naiwen Zhou,Linghan Wu,Ziqiang Wang,Zhihua Wang, A 28-Gb/s Transmitter with 3-tap FFE and T-coil Enhanced Terminal in 65-nm CMOS Technology, NEWCAS 2016, pp. 1 - 4, 2016.

[2] Naiwen Zhou,Ke Huang,Fangxu Lv,Ziqiang Wang,Chun Zhang,Zhihua Wang, A 76 mW 40-Gb/s SerDes Transmitter With 64:1 MUX In 65-nm CMOS Technology, ICEIEC 2016, pp. 155 - 158, 2016.

[3] Naiwen Zhou,Ertai Duo,Ziqiang Wang,Hanjun Jiang,Ke Huang, A 3-Tap Feed-Forward-Equalizer in 65nm CMOS , Microelectronics, pp. 764 - 768 , 2015.

Patents：

[1] Ziqiang Wang, Naiwen Zhou, Fangxu Lv, Chun Zhang, Zhihua Wang, Fule Li. A transmitter with timing alignment: China, 201611104171.4[P]. 2020-10-27.