Biography
Enrollment Date: 2013
Graduation Date：2016
Degree：M.S.
Defense Date：2016.05.31
Advisors：Ziqiang Wang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design and Implementation of a Transceiver Controller based on JESD204B Protocol
Abstract:
The sampling, encoding and transmitting of information is the basic part of a communication system. With the development of the chip-making technology and the continuous improvement in the chip design, the sampling rate and resolution of the ADC / DAC is in rapid growth, and the amount of data transmission of each ADC / DAC in unit time are also in the rapid growth, which bring enormous challenge to the data transmission interface and PCB layout. There are several problems of conventional parallel data transmission as followed. It leads to much more complexity of the PCB layout, the data transmission rate is restricted and the synchronization of parallel data transmission cannot be guaranteed. In order to solve a series of problems emerged, high speed serial interface technology is brought into being. For the ADC/DAC high speed data transmission system, JESD204B protocol formulates corresponding norms, effectively solve the above problems.Based on the JESD204B protocol, this paper designs and implements the transceiver controller module. It is applied to the ADC/DAC high speed data transmission system. Firstly, I carefully read and understand the content of the jesd204b protocol, divide the JESD204B system work process of three stages, comb the work that should be accomplished in each stage, design the modules that can complete the work, and write the RTL code of each functional module. The transmitter controller is improved on the basis of the existing controller. The receiver controller is designed based on the pipeline, which mainly includes code group synchronization module, configuration parameter resolution module, data synchronization alignment module and data descrambling module.In this paper, the verification system is based on the demo project of IP JESD204B core of Altera company. The basic idea is to verify whether my transceiver controller can correctly communicate with the transceiver controller of Altera's. The validation work is divided into two stages. The first stage is to use the Modelsim software to simulate the whole verification system, to verify the functional correctness of the transceiver controller through the comparison of sending and receiving data. The second stage is verified by FPGA development board, using SignalTap II software to crawl and compare the sending data and receiving data to validate the functional correctness of the transceiver controller. The verification results show that the transceiver controller meets the requirements of JESD204B protocol. To verify the interoperability of the transceiver controller and the commercial ADC / DAC supporting JESD204B protocol, this paper makes a further research.