Biography
Enrollment Date: 2013
Graduation Date：2016
Degree：M.S.
Defense Date：2016.05.30
Advisors：Ziqiang Wang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Critical Technology Research for Receiver of Low Power High-Speed Serial Links
Abstract:
Higher data rate and lower power consumption are the two important trends in the development of high speed serial links. As the data rate keeps rising, high speed serial links suffer from design challenges caused by limited bandwidth, heavy channel loss and high power consumption. In this dissertation, the principle and commonly used techniques of high speed serial links’ receiver are introduced and summarized. Focusing on the equalizer, and clock generation and recovery circuits, this dissertation has completed the following researches:
First of all, a 40 Gb/s low power combined equalizer is realized by utilizing and put forwarding multiple optimization techniques. This equalizer consists of the linear equalizer and the decision feedback equalizer. The linear equalizer is implemented by inductive peeking and source degeneration techniques which significantly improve the bandwidth and high frequency gain of the equalizer. The decision feedback equalizer is implemented by closed-loop architecture which has 3 coefficient taps. In the design of the 1st tap, there are three optimization techniques used to relax the timing constraint of the loop path, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Besides, the dissertation first proposes to reduce the charge loss of the dynamic latch in the locking state by using a PMOS. In the design of the 2nd and 3rd taps, there are two optimization techniques used to reduce the power consumption of the loop path, namely a clock-controlled DMUX and a merged feedback MUX and clock-controlled summer arrays, which means the 20 Gb/s data flow of the even path and odd path are deserialized to two 10 Gb/s data flows respectively and then the 10 Gb/s data flows complete serialization and summation at the same time. The combined equalizer is fabricated in TSMC65 nm CMOS technology and the simulation shows that the power consumption is 1mW/Gb/s when equalizing the channel with 30 dB loss.
Moreover, a 40 Gb/s low power adaptive equalizer is realized by utilizing mixed-signal design scheme. The adaptive logic of the equalizer is based on the amplitude approaching technique which means that the data amplitude would approach the reference voltage when the logic adaptively adjusts the gain boost of the equalizer path. The equalizer path is an analog circuit which could provide strong equalization ability. The adaptive logic is a digital circuit which could save lots of power consumption. The design of the adaptive equalizer is based on TSMC65 nm CMOS technology and the simulation shows that the power consumption is 1 mW/Gb/s when equalizing the channel with 20 dB loss.
Last, a 40 Gb/s clock and data recovery circuit is implemented on the basis of a 28 Gb/s clock and data recovery circuit. This circuit is based on the interpolator architecture with lots of optimization techniques. First, the on-chip inductance of samplers in the initial chip is removed which reduces the area of new chip significantly. Second, the supply current of samplers is reduced while the sampling bandwidth is still enough to sample data successfully, which helps the chip to save much power consumption. Third, a complementary phase interpolator architecture is used to improve the linearity of phase interpolating, which reduces the jitter of recovered clocks. Besides, in order to reduce the length of bonding wire, a small hole is digged out for chip package on the testing PCB, which could help reduce the data signal attenuation induced by bonding wire and improve the test of chip. This chip is fabricated in TSMC65 nm CMOS technology and the test showes that the power consumption is 3.8mW/Gb/s with a BER less than when working at 40 Gb/s.