Biography
Enrollment Date: 2013
Graduation Date：2016
Degree：M.S.
Defense Date：2016.05.30
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：An 11-bit 250MS/s Subrange SAR ADC
Abstract:
Pipelined ADC, flash ADC, ∑-Δ ADC and successive approximation register (SAR) ADC all are common-used ADC structures. SAR ADC has been widely used for its low power, high resolution and accuracy, as well as small size. But for an n-bit SAR ADC, there are n comparisons need to be finished in one AD conversion cycle, so it is hard to realize a SAR ADC with high resolution and high speed at the same time. This paper presents an 11-bit 250MS/s subrange SAR ADC. The subrange SAR ADC in this paper consists of coarse conversions of 4-bit flash ADC and fine conversions of 8-bit SAR ADC, which fully combines high speed of flash ADC and low power consumption of SAR ADC. In order to realize a high-performance design of high integration and low power consumption, this article analyzes the key modules of coarse conversions and fine conversions in details. (1) Analyzing the sampling circuit and timing series in flash ADC; the implemented design adopts SHA-less architecture, and optimizes the timing series to reduce the aperture error; bootstrap clock is used in sampling input signal to decrease the nonlinear error; analyzing the interpolation-average structure and its problems in flash ADC. (2) The article summarizes and contrasts the existing methods of eliminating comparator offset, and foreground offset calibration is adopted in this design to minimize the comparator offset to a tolerable level. (3) High-speed dynamic comparator is adopted in SAR ADC; asynchronous clock and logic are used to achieve high conversion speed; segmented capacitor array is used in the design to reduce area and power. (4) Since there is 1 bit redundancy, 1/32 full scale range comparator offset or aperture error can be tolerated. (5) Putting forward a new comparator offset calibration technique, which costs less, and gets small area as well as high speed. Through the simulation result, the 12.7mV offset can be reduced to 2.4mV after calibration. Combining high-speed asynchronous SAR circuit to comparator offset calibration, which speeds up calibration effectively.
The design is fabricated in a smic 40nm low leakage CMOS technology，and schematic and layout design are completed, as well as detailed simulation. The core area is 180μm×100μm. At 250MS/s and 32.7MHz input frequency, schematic simulation result shows ENOB of 11.02 is achieved and ENOB of 10.64 is achieved in post layout simulation result. At Nyquist input frequency, ENOB of 10.99 in schematic simulation result and 10.54 in post layout simulation result are get. Considering the system noise, the ENOB of the ADC drops to 10.03 bits. The power consumption of the ADC core is 1.7mW and the FOM is 6.64fJ/conv-step. The post layout simulation result shows the design has reached the goal of high sampling rate and low power consumption.