Biography
Enrollment Date: 2013
Graduation Date：2016
Degree：M.S.
Defense Date：2016.06.01
Advisors：Chun Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Study and Implementation of
Error Correction Code Circuit for SSD
Abstract:
With the advent of the era of Big Data and Internet of Things (IoT), the storage technology is also improving. As solid state driver (SSD) has the characteristics of fast access speed, high capacity and low power consumption, it is widely used in the cloud servers and personal computers. However, as multi-level cell (MLC) NAND Flash becoming popular and the physical NAND flash memory cell feature size scaling-down, the raw bit error rate (RBER) becomes higher and higher, raising to 10-3 magnitude. The traditional technology of error correcting code (ECC), which base on BCH codes, are no longer powerful enough for MLC NAND Flash. Low density parity check (LDPC) codes are one of the promising replacers for the future NAND flash products. In this paper, we present LDPC encoder and decoder for SSDs.Considering the requirements of SSDs, we design a high-throughput and area-efficient LDPC decoder for NAND Flash memories, supporting multi-rate quasi-cyclic (QC) LDPC codes. This decoder realizes the normalized min-sum algorithm (NMSA) and layered message passing. To support different multi-rate QC-LPDC codes, the decoder is designed with the idea of single instruction multiple data (SIMD) processor for reference. Coordinating with decoder, we design the LDPC encoder with the idea of CPU for reference, which realizes the RU algorithm. We also design the instruction set and the related compiler.In order to meet the high throughput requirement of SSDs, an adaptive normalized min-sum algorithm (NMSA) is implemented. With the proposed technique, an improvement in throughput of around 29.2%~43.4% is achieved when signal-to-noise ratio (SNR) is 6.14dB, and the area overhead is only 0.87%. The LDPC decoder is implemented in TSMC 65nm standard CMOS technology. For a rate-0.889 length-36864 QC-LDPC code, the decoder achieves a throughput of 14.9 Gb/s, and achieves a high area efficiency.Based on Matlab and ModelSim, we build verification environment, and finish the the simulation verification of decoder and encoder. Base on the FPGA board of Xilinx, we finish the verification on FPGA. The LDPC code that used in experiment has a good error correction performance, which can satisfy the RBER of 9×10-3. As the decoder and encoder can support different QC-LPDC codes, if there be any better LDPC code in the future, it would achieve better error correction performance.