Biography
Enrollment Date: 2013
Graduation Date：2016
Degree：M.S.
Defense Date：2016.06.01
Advisors：Hong Chen
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design of a Near-threshold Wide Voltage Standard Cell Library
Abstract:
Multimedia applications such as interactive games posed stringent performance requirements for microprocessors using in mobile application. Meanwhile, the power of microprocessor needs to be lowered in standby mode or other situation for longer battery life. One solution to meet varying performance requirement is near threshold computing. Near-threshold computing brings the promise of an order of magnitude improvement in energy efficiency over the current generation of microprocessors. To enable the processer working at near threshold voltage for better energy efficiency, a digital standard cell library optimized for wide voltage range is necessary for better performance and reliability of microprocessor..
In this paper, the design methodology of developing a standard cell library specific for 0.6V operation in 40nm CMOS technology is presented. An optimized method of sizing sub-threshold cells considering process variation is stated. The library for wide voltage operation is designed and key considerations leading to better cell performance over 0.6V-to-1.1V voltage range are demonstrated. Then the library is characterized and validated with ISCAS’89 and ITC’99 benchmark circuits. Comparison results on power and performance between our library and the foundry-provided one are shown. The 40nm 0.6V standard cell library is used in the SHA processor. Utilizing the standard cell library, the SHA accelerator core scales as synthesized from better performance at 1.1V down to lower power at 0.6V.
(1) At near-threshold voltage, process variation remains the biggest challenge. This paper analyzes cell delay and noise margin variation. Then an optimized method of sizing sub-threshold cells considering process variation is stated. Using this method, unit delay at near threshold 0.6V decreased 4.8% -16.4%, and the mean noise margin improved by 3.9 % -6.6% compared with the commercial library. Based on SMIC 40nm process cells are designed and test circuit layout are drawn.
(2) The cell library is characterized at 0.6V and 1.1V corners for synthesis at near threshold and normal voltage. Four benchmark circuits from ISCAS’89 and ITC’99 benchmark suite were selected to test library performance when synthesizing practical circuit. The benchmark circuits were synthesized using our library and foundry provided one. Evaluation with benchmark circuits show 4.5%-6.9% speed improvement and 6.7%-22.3% less power consumption synthesized at 0.6V compared with the foundry-provided one.
(3) Our near-threshold library is utilized in the implementation of a SHA IP core. The SHA IP is a SHA algorithm accelerator. It is synthesized at 0.54V 125℃ SS corner with corresponding library file. The clock frequency is 5M. Evaluation with SHA core show around 80% less power consumption synthesized at 0.6V compared with 1.1V. The SHA core are taped out and future test on silicon is under-going.