Biography
Enrollment Date: 2013
Graduation Date：2016
Degree：M.S.
Defense Date：2016.05.30
Advisors：Baoyong Chi
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on Key Techniques of Digital Polar Transmitter for Low-Power WiFi Application
Abstract:
Wireless communication plays a very important role in the rapid development of Internet of Thing (IoT). There will be more and more devices need be connected to network and exchange data in the future. The low-power WiFi protocol uses Sub-GHz band, and is low power consumption, multi data rate and multi bandwidth configurable, supporting up to 8MHz bandwidth, which is suitable for application of IoT. The traditional close-loop phase modulation polar transmitter is limited by the bandwidth of the loop filter in PLL, which can only reach the kHz level, so it cannot meet the requirement of low power WiFi applications. This dissertation designs a reconfigurable digital polar transmitter for application of the low-power WiFi, which extends the bandwidth of the phase modulation with open-loop architecture. The transmitter is implemented in digital circuits except for the power amplifier and phase modulator. The effect of interpolation rate, filter characteristics, and quantization on EVM and spectra purity is researched at system level. In consideration of the trade-offs between implementation complexity, power efficiency and performance, a specific design plan is proposed after numerous simulations. This dissertation also make optimization on circuit design level. By using folding polyphase interpolation filter structure, the power consumption is three times efficient compared to direct form realization of FIR. The depth of amplitude and phase pre-distortion look-up table decrease by 75% with appropriate cut off in bits width. By using a new macro-cell structure to implement thermometer encoder, the logical depth is greatly decreased. An open-loop phase modulator with high resolution phase interpolator (PI) provides high bandwidth modulation in phase path. The phase interpolator is implemented with an array of Gilbert mixer cells, which is steered by current DACs. A new method of controlling steering current is investigated, so that the output of PI is constant envelope and the quiescent point is also stable. This dissertation introduce three techniques to improve PI’s linearity: utilizing buffer to suppress the high order harmonics of the local oscillator signal, capacitor compensation to balance the amplitude of I/Q local oscillator signal and digital pre-distortion. The digital circuits and phase modulator is implemented from behavior level to layout in TSMC 65-nm technology. The digital processing circuits have 93,000 standard unit, which is 0.4872um2 with the utilization rate of 74.5%. The power consumption of digital part is 21.3mW in 8MHz bandwidth mode, while only 8.9mW in 1MHz bandwidth mode. The total area of phase modulator is 0.2um2, consuming 12mW. The PI has an average phase step of 0.703 degree, DNL is 0.525LSB. The result of digital circuit and phase modulator co-simulation shows that he transmitter achieves 3.7% EVM. The noise floor and the strongest spectral alias are suppressed below -40dBr without RF filtering, fulfilling the design specification and leaving margin of DPA design.