Biography
Enrollment Date: 2013
Graduation Date：2016
Degree：M.S.
Defense Date：2016.05.30
Advisors：Baoyong Chi Jun Fu
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on Design Technique of Low-Power Reconfigurable Continuous-Time Sigma Delta Modulator
Abstract:
With the development of wireless communication technology, the low-power data rate variable short-range wireless transceiver has become a research hotspot. Due to its high accuracy, inherent anti-alias filtering characteristics and large dynamic range and other advantages, continuous time sigma delta modulator is widely used in the full-integrated wireless communication chip, which could greatly reduce the design complexity and power consumption of the receiver, it is the key factors of the whole receiver circuit.
This thesis proposes a continuous time sigma delta modulator for low-power consumption data rate variable short-range wireless transmission receiver, which could be configured to lowpass / complex bandpass mode in different application. And the configuration technology could optimize power consumption, to improve power efficiency under different modes. The multi-mode reconfigurable CT sigma delta modulator includes reconfigurable loop filter, multi-bit quantizer and DAC array. The corresponding calibration circuits are used to calibrate the nonlinear circuit，thus ensuring the signal to noise ratio and stability of the modulator.
Loop filter with active RC structure. In the low-pass mode configuration with the 3rd-order hybrid structure, and the use of fixed delay of a loop delay compensation to compensate the ELD between the loop quantizer and DAC, enhancing the stability of the system. In complex-bandpass mode with 2nd-order feedback structure, fasten the variable delay between quantizer and DAC, and adding a latch to eliminate effects of the comparator delay on the performance of the modulator. Due to its high tolerance of the loop delay, 2nd-order structure don’t need an extra ELD loop, which could reduce the power consumption of CBP mode. The active feedforward compensation with cascode structure to realize the operational amplifier, to achieve high-speed and high gain dual channel amplifier unit. And the inverse pole splitting technique can expand the bandwidth, to achieve high GBW. The GBW can be configured by an active feed forward cell parallel operation amplifier, which can save area and power consumption. Each integrator stage of the loop filter can be configured to achieve low-pass / complex band-pass reconfigurable, which could reduce the system design complexity and power consumption. The multi-bit quantizer with three cascaded structure, and the DC offset self calibration circuit to ensure low DC offset. DAC arrays with non return to zero NRZ type structure, and the multi bit digital switch to control the DAC arrays, and puts forward the gate leakage compensation and DWA algorithm to improve the gate leakage and random mismatch problem, in order to ensure adequate coverage and high accuracy requirements.
The CT sigma delta modulator implemented in 65nm CMOS technology, and through the simulation after parasitic stripping. Under the low pass 4MHz-BW mode, the modulator achieves 77.2dB SNDR, 82.3dB DR, powered by a 1.2-V supply, the power consumption is 3.24mW, and the simulation FoM value is 38fJ/conv.. In the complex band pass 1MHz/2MHz-BW mode, the modulator achieves 79.6/80.6dB SNDR, 80.7/81.5dB DR, the corresponding power consumption and FoM is 2.96/3.48mW and 167/82fJ/conv., respectively.