Biography
Enrollment Date: 2013
Graduation Date：2016
Degree：M.S.
Defense Date：2016.05.30
Advisors：Baoyong Chi
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on Design Techniques of Reconfigurable Harmonic Rejection
Transmitter for Industry-Specialized Applications
Abstract:
Software-defined radios (SDRs), as an economical solution for multi-mode multi-band transmitters, have recently aroused extensive interest and attention from industry and academia. Industry-specialized communication, one of the important application fields of SDR technology, is widely used in Internet of Things, disaster emergency, rail communication. In order to meet a variety of communication protocols, transmitters need to support a wide frequency range, rendering harmonic rejection a key consideration for the design of SDR transmitters.
This dissertation presents a 0.1-1.5GHz SDR transmitter implemented in 65nm CMOS for industry-specialized multi-standard applications. Since the frequency band is 15x wide, the sidebands generated by harmonic-mixing unavoidably fall in the band. To achieve desired harmonic rejection, a first proposed two-stage harmonic rejection (HR) power mixer is utilized, which can directly drive the power amplifier. The first-stage and second-stage HR are all incorporated into power mixer, and all operate in current mode through current mirror and current division circuits respectively, which, to best knowledge, has not been introduced in previous paper.
The transmitter consists of 10-bit current-steering DAC, trans-impedance LPF (TI-LPF), V-to-I converter, power mixer, RF I-to-V, power amplifier. 10-bit current-steering DAC converts the digital signal to analog, output current of which feeds the reconfigurable TI-LPF with 2nd-order Tow-Thomas structure. The TI-LPF has 0-26dB programmable gain with reconfigurable 3dB bandwidth 3.2M and 5.7M. The V-to-I converter transforms the transmitter operation from voltage mode into current mode, then mirroring the current to the switching pair of power mixer which directly drives CMOS PA. The mirror factor of current mirrors is 2:3:2, realizing the first stage gain ratio. Additionally, a RC pole is inserted into current mirror. Current division technique is employed in HRM load for achieving the second stage gain ratio 5:7:5. The switching pair of HRM is driven by eight equidistant phase LO signals. The RF I-to-V is inverter-based trans-impedance amplifier with programmable gain ratio 1:1:2, which converts the output current of HRM into voltage signal. The 0.1-1.5G CMOS PA has reconfigurable output power with transistors divided into 1:2:3.
The simulated results show that TI-LPF realizes 0-26dB dynamic range and adjustable bandwidth between 3.2M and 5.7M. The proposed power mixer achieves >65dB HRR3 and >68dB HRR5, respectively, over the covered frequency band without any calibration, the simulated OP1dB of which is from 9.4dB to 12.3dB. The simulated OP1dB of PA operating in AB mode is above 19dBm. Besides, the simulated saturation output power of PA operating in F mode is above 23dBm. The SDR Transmitter achieves >75dB HRR3 and HRR5.