Biography
Enrollment Date: 2013
Graduation Date：2016
Degree：M.S.
Defense Date：2016.05.31
Advisors：Baoyong Chi Sheng Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on Design Techniques of Reconfigurable Harmonic Rejection Receiver for Industry-Specialized Applications
Abstract:
Communication technology is growing fast nowadays, mobile terminals supporting 3G、4G、WLAN and other communication standards are increasingly becoming an integral part of people's lives. Industry specialized communication needs is also growing fast the same as public communications, which plays an important role in navigation, exploration, rescue and other fields. The second-generation of industry specialized communication system in our country covers a wide range of frequency bands, leading to a serious harmonic interference problem for common receivers. Harmonic rejection has become a key demand of circuit design to improve receiver performance.
The principle of harmonic mixing is introduced in this thesis, and a configurable harmonic rejection receiver is presented. This receiver is consist of a wideband low-noise amplifier, a harmonic rejection mixer, a IQ calibration circuit, and a lowpass / complex band-pass filter, it is able to work under both zero-IF and low-IF receiver architecture. The system specifications of receiver derives from communication systems, and then assigned to each circuit module.
The thesis proposes a configurable wideband low noise amplifier with negative resistor feedback, fulfilling a broadband input matching. The principle of harmonic mixing is analyzed in details, and then a mixer strcture for harmonic rejection is introduced. Calibration module is added in order to eliminate the amplitude mismatch and phase mismatch effects of harmonic rejection. The mixer shows effectively rejection of 3rd/5th harmonic interference, and can achieve good switch of operating modes.
A low-pass/complex band-pass filter is implemented based on the 5th order Butterworth low-pass filter, which is able to support zero-IF and low-IF receiver architecture. IQ calibration circuit is set in front of filter to calibrate the amplitude mismatch and phase mismatch, resulting in a good image rejection for the receiver.
The proposed receiver front end has been implemented in 65nm CMOS process. The simulation results show the system achieves a gain range of 11dB-64dB, noise figure less than 5dB, IIP3 higher than 0dBm, 3rd/5th order harmonic rejection rate more than 40dBc/60dBc with/without calibration. Analog baseband provides 6 dB/9 degrees gain/phase calibration range, and achieves a low-pass/complex band-pass filter characteristic with five tunable bandwidth.