Biography
Enrollment Date: 2012
Graduation Date：2015
Degree：M.S.
Defense Date：2015.09.23
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design of High Speed Serial Interface Controller Based on JESD204B
Abstract:
In our era, the increasing of demand for high data rate application is never stop. This trend leads to the development of high resolution and high sample rate ADC devices. Because of this rapid development, how to transmit a large amount of date generated by data converter has become an important issue. In such a situation, the interface system of data conveter is becoming the bottleneck of modern applications. To solve this problem, the interface of data conveters begin to transfer from traditional parallel form to high speed serial form. By considering the cost of pin density of packaging, power efficiency, the layout complexity on PCB and the flexibility to connect with an optic-fiber communication system, in the field of high performance applications, the design of high speed serial interface is always a hotspot issue. The industry has developed a lot of HSSI protocols and a protocol called JESD204B has been proposed by JEDEC committee which is designed for high speed serial data transmission between data converter devices and FPGA.This paper give an interpretation to the JESD204B protocol and propose a specific implementation of HSSI transmitter controller in RTL level based on this protocol. The controller contains transport layer and data link layer of JESD204B. It can be used as transmitter interface controller of ADC devices or FPGA. Besides that, this paper also gives a discussion about methdology of digital logic circuits design and techniques of high speed low power digital circuit design. It is verified with the JESD204B Receiver IP core and Transceiver Native PHY IP provided by Altera. The verification includes function simulation based on Modelsim and function verification based on FPGA development kits, by communication with Receiver IP core, it proves that the controller this thesis designed fits the requirements of JESD0204B protocol.