Biography
Enrollment Date: 2012
Graduation Date：2015
Degree：M.S.
Defense Date：2015.06.03
Advisors：Liji Wu
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design and Implementation of Adaptive Equalization Circuit for High Speed Serial Link
Abstract:
As the start of data-intensive applications, such as big data, cloud computing and 5G, data transmission rate is becoming very high. High speed serial interface circuit design has become the core of high-speed data interconnection design, and signal integrity is one of the biggest challenges. Reflection and distortion caused by impedance mismatch and inter-symbol interference induced by channel attenuation seriously affect the quality of signal transmission. Equalization technology, especially adaptive equalization technology, is widely used in the high-speed serial link.In this paper, for the next generation 100G Ethernet PHY interface and high performance computer, the transceiver adaptive equalization technique is studied. First, the channel is analyzed and characterized. By analysis of the channel parameters of time domain and frequency domain, the signal loss in the high frequency is very serious, and the equalization must be adopted in sender and receiver in order to improve signal quality.This paper aimed at the implementation of the adaptive equalization.The adaptation algorithm for adaptive equalization is studied. Firstly, this article introduces the design of the receiver adaptive equalization. To verify the adaptive algorithm of receiving end, a 25 Gb/s quarter rate structure of the decision feedback equalizer is designed, and provides data and error interface. The mainstream adaptive algorithm (Sign-Sign Least Mean Square, SSLMS) has been realized for the decision feedback equalizer, and the digital logic is finished by full custom implementation, working at 1.5625 GHz. The 25 Gb/s adaptive equalization design has been achieved in TSMC 65nm CMOS technology, and testing results show that the adaptive equalization can automatically compensate the channel attenuation, and with a 20dB compensation. Then key technology of the adaptive equalization for the sending end of 40Gb/s circuit is researched, using the combination of FFE and CTLE equalization. FFE has 4 tap, and the adaptive algorithm of Zero Forcing is used for the adaptive regulation. The design is also implemented by TSMC 65nm process, and the circuit has been taped out and being tested.