Biography
Enrollment Date: 2012
Graduation Date：2015
Degree：M.S.
Defense Date：2015.06.03
Advisors：Chun Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design of Error Correction Code Circuit and Compiler for SSD Controllers
Abstract:
Solid state drivers (SSDs) have play an important role in the cloud server and the terminal PC in recent years. With tremendous growth of the storage capacity and widely use of the MLC/TLC Flash memory chips, the possibility of SSD data error is also growing under the current technology. In order to reduce the error rate of data and improve data reliability, we need to design a high performance error correcting code (ECC) circuit in SSD controller chips.
In this paper, BCH error correction algorithm is used to design a maximum capacity of 72bit/1KB ECC circuit based on the current product requirement and research situation. The parameter of this code is BCH (9193, 8192, 72) according to the encoding rules. In the encoder module, a 32-bit parallel LFSR structure is employed, which improve encoding efficiency by using the same amount of registers. In terms of the three main modules of the decoder, syndrome computation (SC) module multiplex encoder structure to reduce the complexity, and the method of time-sharing computing cut down circuit area; BM algorithm module hires simple inversion-free Berlekamp-Massey (SiBM) algorithm, so that the number of iterations is reduced from 144 to 72. Moreover, finite field multipliers are time-sharing multiplexed in each iteration cycle, and pipeline operation with the SC module is also used; Chien search module fulfile the optimal search by changing the search location and early termination mechanisms, and sharing common-sub-expressions (CSEs) are introduced to lower hardware complexity and design the 32-bit parallel search circuit. The decoder circuit’s data throughput can reach 3.2 Gb/s and it will occupy 119.5K logic gate counts using TSMC 65nm technology, and the decoding latency is also reduced to 2.92us by these optimization method.
The entire circuit is mounted onto NiosII processor to build SoPC software and hardware co-verification system. Altera's StratixV series FPGA chip is used to complete the verification, BCH circuit portion occupies 43K logic elements.
On the basis of BCH circuit design, the paper also designs an IP core compiler, so that subsequent developers can simply configure the relevant parameters and generate RTL code of BCH circuits automatically to meet the needs of different application scenarios, which will greatly shorten the development cycle.